An eight-channel acquisition design sampling each channel at 125 MSPS and 14 bits produces 14 Gb/s of sample data before framing. This guide uses that explicit workload to evaluate XC7Z030-1FBG676C. It does not claim an implemented board or guarantee that a particular ADC interface or filter bank fits.
Start with the end-to-end data budget
| Data representation or path | Calculated rate | Consequence |
|---|---|---|
| Eight channels × 125 MSPS × 14 bits | 14 Gb/s = 1.75 GB/s, packed | This is payload alone; protocol and alignment overhead may increase it. |
| Samples padded to 16-bit words | 16 Gb/s = 2.00 GB/s | Budget the format actually stored or transferred. |
| Write padded samples to DDR and read them once | 4.00 GB/s of aggregate payload traffic | This excludes command inefficiency, refresh and competing traffic; it is not an achieved DDR rate. |
| 1 Gb/s Ethernet line rate | 125 MB/s before protocol overhead | Cannot carry the continuous raw stream. Packed data needs more than a 14:1 reduction; padded data more than 16:1. |
Choose explicitly between finite burst capture, local continuous processing and continuous remote streaming. Changing a DMA setting cannot remove a sustained bandwidth deficit. A FIFO only postpones overflow when average input exceeds average output.
Check silicon resources and buffering time
DS190 lists Kintex-7-class PL, 400 DSP slices and 265 × 36 Kb block-RAM blocks, or 9.3 Mb in its resource summary. The device does not have 360 DSP slices or 7.7 Mb of block RAM. For -1C, DS191 limits the CPU to 667 MHz with the 6:2:1 ratio or 533 MHz with 4:2:1; do not use an 866 MHz budget.
The arithmetic capacity of all 265 × 36 Kb blocks is 1,221,120 bytes, including bits whose usability depends on the chosen memory configuration. Even if every bit could buffer samples, this would hold only about 0.70 ms of packed traffic or 0.61 ms of padded traffic. Actual buffering is less after allocating FIFOs, processing state and configuration overhead.
FBG676 provides 100 HR and 150 HP PL I/O plus four GTX channels, separately from the PS interfaces. Confirm the channel count, data width, clocks and bank compatibility of the selected ADC connections; the total I/O number is not a proof that eight ADCs can be connected.
Manufacturer references: DS190: Zynq-7000 overview, Tables 1 and 3; DS191: Z-7030 electrical specifications and CPU clock Table 19.
Design the input clock and sample alignment
- Record each ADC’s exact output mode, signaling levels, lane count, data clock and framing requirements from its own datasheet. A serial converter link and a parallel source-synchronous bus require different receiver designs.
- Allocate pins and banks together with their supplies and reference/termination requirements. Do not treat HP banks as 3.3 V general-purpose inputs.
- Define the channel-to-channel timing requirement and distribute clocks/triggers accordingly. Validate sample alignment after startup and recovery, not just nominal clock frequency.
- Capture a documented ADC test pattern before interpreting analog measurements. Check lane mapping, word boundaries, polarity and alignment.
- Preserve channel identifiers and timestamps or sample counters through the pipeline so dropped or reordered data can be detected.
GTX availability alone does not establish support for an ADC’s chosen high-speed protocol. FBG676 has a 6.6 Gb/s package ceiling, and the receiver needs a supported protocol/IP configuration, reference clocks and electrical design.
Manufacturer references: DS190: Zynq-7000 overview, Tables 1 and 3; UG933: Zynq-7000 PCB Design Guide.
Make data reduction an explicit signal-processing choice
If the application needs a lower-rate band or summary rather than every raw sample, define the required passband, stopband, alias rejection and numerical precision before implementing decimation or digital downconversion. Discarding samples without suitable filtering is not a generally valid substitute for decimation.
Budget arithmetic using the actual filter topology, taps, channel count, input rate and processing clock. Time sharing may save DSP slices, but only if the scheduled operations meet every sample deadline. Coefficient symmetry, pipeline depth and precision affect the implementation; 400 DSP slices do not translate into a universal maximum filter length.
Keep an overflow and rounding policy for each stage. Verify against a numerical reference with chosen test signals, including full-scale and out-of-band inputs. State whether the output is raw samples, filtered samples, FFT results or application features; each has a different traffic and validation budget.
Prove the memory and output path under contention
For external-memory capture, calculate the number and size of DMA buffers, the permitted capture duration and how full/empty states are handled. Reserve memory safely and use the platform DMA/cache interfaces. Cache maintenance, descriptor ownership and interrupt handling must agree with the hardware data path.
Measure sustained transfers using the final memory width, clock, burst pattern and simultaneous traffic. A standalone sequential memory benchmark can overstate what acquisition achieves while processors, network traffic and processing blocks compete for memory.
Select an output interface whose useful payload rate meets the reduced stream, or document the allowed duty cycle of burst uploads. Account for backpressure and disconnects. A functioning link is not evidence of lossless sustained acquisition.
Bring up power, boot and diagnostics before full-rate capture
Use the actual Zynq-7000 supply names and limits in DS191. Names such as VCC_PSINTFP belong to a different family and must not be used to define this board’s rails. PL, PS, I/O and GTX requirements are distinct, with documented sequencing and reset constraints.
FBG676 is a lidless BGA package; do not design a QFN-style central underside thermal pad from a generic description. Choose the power architecture, stackup and thermal solution from calculated and measured requirements rather than assuming one named PMIC or a fixed layer count solves every design.
Bring up the processor, reserved-region DDR diagnostics and low-rate transfers first. Add the ADC test stream, processing and final output in controlled stages. Include counters for FIFO overflow, DMA errors, link errors and lost samples; arrange ILA triggers to capture failures without claiming that a CPU breakpoint stops all PL logic.
Manufacturer references: DS191: Z-7030 electrical specifications and CPU clock Table 19; UG865: package, pinout and FBG676 mechanical drawing; UG1283: BootROM, FSBL and boot-image flow.
Acceptance evidence for an acquisition release
- A reconciled input, processing, memory and output bandwidth worksheet.
- A timing and resource report for the implemented processing design.
- Known-pattern and numerical-reference results with explicit precision and error limits.
- Sustained-load runs stating duration, sample counts and error/drop counters.
- Verified startup alignment, reset recovery, backpressure behavior and overflow reporting.
- A versioned hardware/FSBL/bitstream/software configuration and measured operating conditions.
Related engineering tasks
- Exact-device specifications and sourcing checks
- Boot, DDR, AXI and serial-link troubleshooting
- Machine-vision acquisition and inspection planning
- Board design-in with HR/HP I/O and GTX links
- Replacement and migration approval checklist
For sourcing, send the complete XC7Z030-1FBG676C ordering code, quantity, required date and documentation needs through Request a quotation. Price, availability, delivery and other commercial terms are confirmed in each written quotation.
Technical review: 8 October 2026, using the linked manufacturer documents. Calculations are stated planning examples; no WWDParts hardware test or certification is claimed.