Use this checklist to take XC7Z020-2CLG400C from architecture selection to a controlled first-board bring-up. It identifies decisions and evidence to record; it is not a finished schematic or a board that has been validated by WWDParts.
1. Decide whether the PS/PL split solves your problem
List the software functions, data rates, external interfaces and worst-case response times before selecting the device. Put operating-system services, networking and configuration in the PS where appropriate. Consider PL implementation for parallel datapaths and event timing that software alone cannot meet. Measure the cost of transferring data as well as the cost of processing it.
| Architecture option | Decision to test |
|---|---|
| MCU or application processor | Can existing peripherals and software meet the load without custom logic? |
| Processor plus separate FPGA | Does an external link meet throughput/latency needs, and is independent selection of the two devices valuable? |
| Zynq-7000 PS plus PL | Does on-chip integration justify the HDL, software, power and PCB work? |
No option is automatically cheaper, lower-power or faster. Compare an implemented workload, supported software, development effort and lifecycle needs. The design cases in the motion-control and machine-vision articles use different budgets and should remain separate.
2. Freeze the part and the pin budget
Use the exact device/package in the design tools: XC7Z020, CLG400, speed grade -2, commercial grade. The package is 17 × 17 mm at 0.8 mm pitch and provides 125 PL HR I/O. The 200-I/O CLG484 allocation does not transfer to this footprint. There are no PL HP I/O banks in this combination.
- Create a pin worksheet with signal, ball, bank, I/O standard, bank supply, direction and clock requirement.
- Allocate DDR and PS MIO functions separately from PL signals; resolve multiplexing conflicts before layout.
- Check special-purpose, configuration, reference and unused-pin connections against UG865, then run the tool I/O rule checks.
- Reserve debug and measurement access. Record the chosen oscillator, boot source and recovery route.
Manufacturer references: DS190: Zynq-7000 SoC overview, Tables 1–2; UG865: packaging, pinout and mechanical drawings.
3. Design supplies and reset together
Use the DS187 rail names: PS core VCCPINT; PS auxiliary VCCPAUX and VCCPLL; PS I/O VCCO_MIO0, VCCO_MIO1 and VCCO_DDR; PL supplies VCCINT, VCCBRAM, VCCAUX and VCCO. Avoid names copied from a different SoC family. Choose a PMIC or discrete regulators by voltage, load, startup and sequencing requirements; the label “FPGA PMIC” is not a compatibility test.
DS187 describes separate PS and PL sequencing. Its recommended PS order is core, then auxiliary/PLL, then PS I/O. Its recommended PL order is core, block RAM, auxiliary, then PL I/O, with specified equal-voltage cases allowed to ramp together. The two regions are independent; do not turn these into a single invented PS-versus-PL order.
Keep PS_POR_B asserted as specified while required supplies rise, and check its release timing against the PL-related secure-lockdown window in DS187. Review power-down and brownout behavior as well as startup. Capture the rails, reset and reference clock together on a prototype; a DC meter reading alone cannot show the sequence.
Manufacturer references: DS187: Z-7020 electrical and switching specifications, Tables 2, 17 and power/reset requirements.
4. Resolve DDR, boot and clocks before routing
Select the exact memory part and bus width, then configure the PS controller for that geometry, timing and board routing. Use the memory manufacturer’s limits together with UG933. A development-board DDR preset is useful only when its assumptions match your board. Do not replace these constraints with “match every trace within 5 mils”.
For the usual boot flow, BootROM copies the FSBL from the selected boot device into on-chip memory and transfers control to it. The FSBL uses the hardware configuration to initialize the PS, optionally programs the PL and hands off to the next application or loader. The FSBL is not code permanently stored in BootROM. UG1283 also describes supported execute-in-place exceptions.
Keep the hardware export, FSBL, bitstream and software platform from a consistent build. Check boot-device compatibility and image layout; retain a recovery procedure. Configure the PS reference clock and derived clocks against DS187. For -2, the CPU maxima are 766 MHz at 6:2:1 and 600 MHz at 4:2:1; timing closure is still required for PL paths.
Manufacturer references: UG933: Zynq-7000 PCB Design Guide; UG1283: Zynq-7000 boot and configuration; UG821: first-stage bootloader responsibilities.
5. Review physical implementation without a generic PCB recipe
Agree the stack-up, escape routing, impedance and return paths with the PCB fabricator. The BGA pitch alone does not mandate a universal layer count, microvias or via-in-pad. Verify manufacturability with the chosen pad/via rules and routing density. Import the manufacturer’s package drawing rather than inventing a central exposed thermal pad.
Use the device/package decoupling guidance in UG933 as the starting point for the PDN, then assess capacitor characteristics and placement. Check DDR routing constraints, discontinuities and bank supplies in a documented review. Estimate power with the actual clocks and activity assumptions; update the estimate after implementation. Evaluate junction temperature with the board, enclosure and airflow. Commercial-grade operation requires the junction, not just room air, to remain in range.
Manufacturer references: UG933: Zynq-7000 PCB Design Guide; UG865: packaging, pinout and mechanical drawings.
6. Bring up one dependency at a time
| Stage | Evidence to collect before proceeding |
|---|---|
| Unpowered inspection | Assembly/orientation, shorts and rail resistance checked against the board design. |
| Power and reset | Recorded rail startup/shutdown, reset release and PS clock meet the selected device requirements. |
| Debug connection | Stable device identification with the intended cable, reference voltage and permitted security/debug state. |
| Minimal software | A deliberately small diagnostic reports its build identity through the intended UART or debugger. |
| DDR | A non-destructive-to-running-code memory test passes across reserved test ranges and intended conditions. |
| Minimal PL peripheral | Register read/write, clocks, reset and address map work before DMA or application traffic is added. |
| Application workload | Throughput, response-time distribution, supply margin, temperature and recovery behavior meet written acceptance criteria. |
A passing UART print does not validate DDR, and a passing memory test does not validate a camera or motion-control path. Preserve logs for each stage so a later failure can be tied to a known hardware/software revision. Use the troubleshooting guide when a dependency fails rather than changing several subsystems at once.
Continue your design review
- Device specifications and ordering checks
- Boot, DDR and AXI troubleshooting
- Three-axis motion-control planning
- Machine-vision bandwidth planning
For a sourcing request, include XC7Z020-2CLG400C, quantity, required delivery date and any lot or documentation requirements. Request a quotation. Availability, price, delivery and other commercial terms are confirmed in each written quotation.
Technical content reviewed against the linked manufacturer documents on 8 October 2026. Application calculations are planning examples, not measurements from a tested WWDParts board.