For a proposed XC7Z010-1CLG400I smart camera, determine sensor capture rate, memory traffic and delivery deadline before selecting an image-processing pipeline. This worked planning guide covers inspection and networked camera uses. It does not establish a tested camera, an OpenCV frame rate or GigE Vision compliance.
1. Turn the inspection task into a data budget
Record active resolution, pixel format, frame rate, sensor blanking, exposure timing and the latest acceptable result time. Separate a trigger-to-decision deadline from sustained frames per second. A fast average frame rate can still miss the conveyor rejection window. Decide whether software needs every full frame, a cropped region or only features extracted in PL.
| Illustrative format at 1920 × 1080, 30 fps | Bytes per active frame | Active payload rate |
|---|---|---|
| 8-bit monochrome | 2,073,600 bytes | 62.208 MB/s |
| Packed 12-bit Bayer | 3,110,400 bytes | 93.312 MB/s |
| 24-bit RGB | 6,220,800 bytes | 186.624 MB/s |
These are arithmetic examples using width × height × bits per pixel ÷ 8; MB means 1,000,000 bytes. They exclude blanking, bus padding and protocol overhead. If a 12-bit sample is stored in a 16-bit word, memory traffic becomes 124.416 MB/s before extra passes. Use the actual DMA stride rather than the packed wire format for memory budgeting.
2. Check the sensor electrical interface
Z-7010 has HR SelectIO and no GTP/GTX transceivers; the XC7Z010 CLG400 allocation is 100 PL HR pins. Check the sensor clock rate, input standard, bank voltage, clock-capable pins and pin count against DS190 and UG865. A parallel interface still needs timing constraints and a verified capture circuit.
MIPI CSI-2 is not automatically a direct connection to generic LVDS pins. AMD PG232 hardware validation states that 7-series devices lack native MIPI IOB support and points to D-PHY solutions. Select an electrical D-PHY implementation or external bridge supported for the chosen sensor, lane rate and IP version. ZC702 demonstrations are not proof that the exact XC7Z010-1CLG400I implementation fits or meets timing. Check IP support and licensing before committing the connector.
3. Partition the pipeline and size buffers
Use PL for bounded streaming operations such as capture, line-based filtering and region extraction, while software manages configuration, higher-level decisions and communications. This is an architecture option, not a guarantee that debayering, OCR and a network stack meet the required deadline together. Start with a measured software baseline and move the bottleneck that justifies its FPGA resource cost.
DS190 gives 60 × 36 Kb BRAM blocks and 80 DSP slices. A 1920-pixel line at 8 bits is 1,920 bytes; two retained lines for a 3 × 3 streaming window hold 3,840 bytes before implementation overhead. A complete 8-bit 1080p frame is over two million bytes and cannot fit in the approximately 2.1 Mb BRAM resource. Use external memory for full-frame storage; reserve BRAM for line buffers and FIFOs, accounting for block geometry, parity bits and other IP.
Size a FIFO from the maximum downstream pause as well as the average rate. At 62.208 MB/s, a hypothetical 100 µs pause requires at least 6,221 bytes of storage before margin. This is a planning calculation: measure or bound the real pause, including arbitration and software delays, then define what happens when the bound is exceeded.
4. Include all DDR and DMA traffic
A frame written once by PL and read once by software already creates two frame transfers; an intermediate RGB image or network copy can add more. Sum each read/write pass, buffer stride and concurrent CPU traffic. Use an appropriate AXI DMA or VDMA configuration and the PS high-performance path where applicable, with correct clocks, resets, address ranges and interrupts.
A DMA engine does not remove software ownership or cache requirements. Define when a buffer belongs to capture, processing and transmission, and do not reuse it while another consumer is active. Apply the operating system DMA API or the documented bare-metal cache operations. UG585 ACP discussion distinguishes coherent access from HP-port behavior; coherence must be configured, not inferred from an AXI connection.
5. Treat Ethernet as a separate capacity check
One 1 Gbit/s link has an ideal raw ceiling of 125 MB/s, before Ethernet and transport overhead. The example 186.624 MB/s RGB stream therefore cannot be sent uncompressed over a single such link at full rate. Even the lower Bayer or monochrome payloads need measured headroom for packet overhead, host response and loss handling. Options include reducing frame rate or region size, packing samples, processing locally or using a justified compression path.
A PS Ethernet MAC needs suitable external PHY circuitry and driver configuration. GigE Vision behavior additionally needs the corresponding software protocol implementation and verification; selecting a Gigabit PHY alone does not make a camera compliant. Test packet loss, reconnects, receiver backpressure and long-duration operation with the production image format.
6. Validate capture through decision delivery
- Use sensor test patterns first. Check line length, frame length, sample ordering and error counters before adding image algorithms.
- Compare PL results with a software reference for known images, including borders, saturation and rounding.
- Exercise DMA buffer rollover, dropped-frame handling and late consumers; log sequence numbers and timestamps.
- Measure exposure/trigger to inspection result and, where used, actuator output. Test deadline behavior under maximum network and CPU load.
- Complete power, temperature, restart and interface tests using the actual PCB. Obtain DDR and reset constraints from UG933 rather than a generic layer count or capacitor list.
Related engineering guides
Board design checklist · DMA and AXI diagnostics
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Technical review: 9 October 2026. The guidance is based on the linked manufacturer documents. Planning calculations and diagnostic steps are not claims of a WWDParts-tested board or application.