XC7Z020-2CLG400C combines a dual-core Arm Cortex-A9 processing system with Zynq-7000 programmable logic. This guide separates device resources from package limits so you can check a BOM, compare an alternative and request the correct ordering code.
Specifications for the exact ordering code
| Item | XC7Z020-2CLG400C | How to use it |
|---|---|---|
| Processing system | Dual-core Cortex-A9 | Software workloads share memory and interconnect resources; two cores do not guarantee a real-time deadline. |
| CPU frequency limit, -2 | 766 MHz in 6:2:1 mode; 600 MHz in 4:2:1 mode | DS187 Table 17. These are clock-domain limits, not a guaranteed application throughput. |
| PL resources | 85K logic cells; 53,200 LUTs; 106,400 flip-flops | Use implementation reports, not logic-cell count alone, to check that a design fits. |
| PL memory and arithmetic | 140 × 36 Kb block RAM; 220 DSP slices | DS190 lists block RAM as 4.9 Mb. Bit capacity is not the same as megabytes of external DDR. |
| Package | CLG400; 400 balls; 17 × 17 mm; 0.8 mm pitch | Check the UG865 ball map and drawing before footprint approval. |
| Package I/O | 125 PL HR I/O; 128 PS I/O in the package table | PS I/O includes dedicated interfaces; it is not 128 freely interchangeable GPIO. This package has no PL HP I/O banks. |
| Temperature grade | Commercial: junction temperature 0°C to 85°C | Budget self-heating. An ambient temperature within this range alone does not establish compliance. |
Manufacturer references: DS190: Zynq-7000 SoC overview, Tables 1–2; DS187: Z-7020 electrical and switching specifications, Tables 2, 17 and power/reset requirements; UG865: packaging, pinout and mechanical drawings.
Read the suffix before comparing parts
XC7Z020 identifies the device; -2 is its speed grade; CLG400 identifies the package; the final C identifies the commercial temperature grade. Keep the complete code in the BOM and quotation. Changing package, speed or temperature suffix can change board, timing or qualification requirements.
The 200 PL I/O figure sometimes quoted for XC7Z020 belongs to CLG484, not CLG400. Neither a family headline nor the number of BGA balls is a usable signal-pin budget. Allocate clocks, voltage banks and special-function pins before accepting a proposed replacement.
What the PS and PL each provide
Use the processing system for software and its fixed peripheral controllers; use the programmable logic for custom datapaths, interfaces and control. The PS includes 256 KB of on-chip RAM. External DDR is a separate board component and is normally needed for a Linux system and substantial data buffers. It is not mandatory for every small on-chip-memory program.
The on-chip AXI connections let software control PL registers and let PL masters access system memory. The design still needs correct address decoding, clocks, resets and buffer ownership. An on-chip connection does not remove contention or turn a software driver into a hard real-time path.
A peripheral controller is not a complete external interface: Ethernet and USB designs require the appropriate board-side physical interface. Likewise, camera compatibility must be established from the selected sensor, receiver implementation and electrical standard.
Power and timing checks before ordering
For this standard -2 device, the nominal internal PS and PL core supplies are 1.0 V; auxiliary supplies are 1.8 V. I/O supply choices depend on the selected interfaces. Treat the rail names and limits in DS187 as separate requirements; there is no single voltage that powers every device pin.
Check the implemented clock configuration against DS187 and timing closure against the exact tool part. A -2 designation is not a blanket 866 MHz CPU rating, and a CPU limit does not set the allowable frequency of every PL circuit. Select regulator capacity from the intended workload and startup requirements rather than the device name alone.
Can another Zynq-7000 part replace it?
- Compare the exact package ball functions using UG865. A package name match is only the beginning of the check.
- Recheck I/O count and bank assignments. For example, DS190 lists 100 PL HR I/O for XC7Z010 in CLG400, versus 125 for XC7Z020 in CLG400.
- Rebuild for the candidate device and inspect logic, DSP, memory, timing and power reports. Do not assume an existing bitstream can be reused.
- Review software hardware definitions, boot configuration, operating-temperature needs and any product qualification obligations.
- Approve the alternative in the engineering BOM before asking procurement to substitute it. A sourcing suggestion is not a compatibility approval.
Pricing and delivery: information to request
A useful quotation states the full ordering code, quantity break, currency, package/lot requirements and delivery conditions. No current price or stock level is asserted here. Historical distributor prices are not WWDParts offers, and a device datasheet does not establish today’s availability.
Ask for the documents your build requires and agree inspection, shipment and acceptance terms in the written quotation. Do not infer an authorized-distributor relationship, guaranteed authenticity or a fixed delivery time from a technical article.
Continue your design review
- Board design-in and bring-up checklist
- Boot, DDR and AXI troubleshooting
- Three-axis motion-control planning
- Machine-vision bandwidth planning
For a sourcing request, include XC7Z020-2CLG400C, quantity, required delivery date and any lot or documentation requirements. Request a quotation. Availability, price, delivery and other commercial terms are confirmed in each written quotation.
Technical content reviewed against the linked manufacturer documents on 8 October 2026. Application calculations are planning examples, not measurements from a tested WWDParts board.