This guide considers an XC7Z020-2CLG400C inspection system that acquires images, processes pixels in programmable logic and passes results to software. It focuses on interface feasibility, buffering and throughput calculations. It is not a completed camera board or a benchmark demonstrating a particular resolution or frame rate.
Start with the camera interface, not a generic FPGA connection
Record the sensor’s output protocol, lane count, electrical levels, clocking, pixel format and peak lane rate. “MIPI CSI-2” and “LVDS” are not interchangeable names for a signal that can always connect to a spare I/O bank. Choose a receiver/bridge implementation supported for the exact device, package and tool/IP version.
AMD’s PG232 v5.1 hardware-validation page describes external Meticom D-PHY I/O in its 7-series interoperability designs. That is evidence against promising an arbitrary CSI-2 camera can connect directly to CLG400 I/O. It is not a recommendation that one bridge fits every current sensor. Check the selected receiver’s implementation guidance and electrical requirements before committing the schematic.
Manufacturer references: PG232 v5.1: MIPI CSI-2 receiver hardware validation.
The CLG400 package is 17 × 17 mm with 125 PL HR I/O and no PL HP I/O banks. Budget clock-capable pins, voltage-bank conflicts and the other board interfaces. A pin allocation from CLG484 or another Zynq device must be redone for this package.
Manufacturer references: DS190: Zynq-7000 SoC overview, Tables 1–2; UG865: packaging, pinout and mechanical drawings.
Calculate pixel traffic and frame storage
For a planning example, assume 1920 × 1080 active pixels, 60 frames per second and one stored 8-bit channel. The active-pixel payload is 1920 × 1080 × 60 × 1 = 124,416,000 bytes per second, about 124.4 MB/s. One packed frame occupies 2,073,600 bytes; two occupy 4,147,200 bytes. These are arithmetic results, not achieved device performance.
If each stored pixel uses three 8-bit channels, multiply those storage and payload figures by three. Include stride/alignment, additional planes, metadata and memory copies in the real allocation. The camera link may carry blanking and protocol overhead that are absent from this active-pixel calculation.
One complete write and one complete read of the 8-bit frame stream already imply about 248.8 MB/s of payload traffic at the assumed frame rate. Display, CPU accesses, other DMA clients and extra processing passes add traffic. Compare the complete traffic budget with measured sustained throughput under contention, not a bus’s theoretical width-times-clock figure.
Choose line buffers, frame buffers and PS/PL responsibilities
The device has 140 × 36 Kb block RAM blocks, listed as 4.9 Mb in DS190. This is not 4.9 MB and does not hold the example 2.07 MB frame. Local filtering may use line buffers, while operations needing whole frames or multiple frames normally require external memory in this example. Calculate each buffer from pixel width, image width and the algorithm’s neighborhood.
| Stage | Design decision |
|---|---|
| Acquisition | Validate the receiver, pixel packing, line/frame boundaries and behavior on malformed or missing data. |
| PL pipeline | Choose operators and arithmetic widths, then measure resource use, latency and timing closure. |
| Frame transfer | Define memory layout, DMA lengths, ownership and backpressure/overflow behavior. |
| PS analysis and communication | Choose which results cross into software; avoid copying full frames when a smaller result set meets the requirement. |
| Inspection output | Carry timestamps or frame identifiers so a decision is associated with the correct observed item. |
The available DSP and logic counts are capacity indicators, not proof that multiple cameras or a particular vision algorithm fit. Similarly, two processor cores do not automatically isolate time-critical work from interrupts, cache effects or memory contention.
Make the memory and transfer path observable
- Start with a known test pattern before connecting a camera. Verify pixel order, stride, frame length and boundaries.
- Give each buffer an explicit producer and consumer. Do not overwrite a frame still being processed.
- Use the platform’s DMA and cache-management facilities correctly. A memory transfer through an HP port is not automatically coherent with CPU caches.
- Expose frame counters, overflow/error flags and completion timestamps. Use ILA or appropriate instrumentation for stream handshakes and frame markers.
- Define whether overload drops frames, stops acquisition or reports a fault. Silence is not an acceptable indication that every frame was processed.
Manufacturer references: UG585: Zynq-7000 Technical Reference Manual.
Review the supporting board before performance tuning
Configure the PS DDR controller for the actual memory and routing. Follow UG933 together with that memory’s documentation; a universal “5 mil matching” rule or copied board preset is insufficient. Generate a consistent hardware export, FSBL and software image. Use the separate power/reset requirements in DS187 and evaluate power with the intended acquisition and processing activity.
For this -2 speed grade, DS187 limits the CPU to 766 MHz in 6:2:1 mode or 600 MHz in 4:2:1 mode. Those limits do not establish a camera throughput. Temperature, supply integrity, DDR margin, receiver support and implemented timing all need their own checks. Thermal design must use the real package/board; do not add an imaginary exposed ground paddle to the BGA footprint.
Manufacturer references: DS187: Z-7020 electrical and switching specifications, Tables 2, 17 and power/reset requirements; UG933: Zynq-7000 PCB Design Guide.
Acceptance tests for an inspection workload
- Compare generated test patterns with captured frames, including the first and last pixels of each line.
- Measure sustained frames per second, dropped frames and end-to-end latency with the real software and competing network/storage traffic.
- Check numerical accuracy against a reference implementation and a representative image set; record data widths and rounding choices.
- Test sensor disconnect, malformed frames, stalled consumers and buffer exhaustion; confirm controlled recovery.
- Test the intended operating range and record power/temperature behavior under the worst representative workload.
- Keep the sensor configuration, receiver/IP version, hardware export and software build with the results.
A project may satisfy average throughput while missing a maximum decision-time requirement. State both acceptance criteria where they matter. Procurement of the SoC and camera components follows engineering selection; a stock listing alone does not demonstrate electrical or application compatibility.
Continue your design review
- Device specifications and ordering checks
- Board design-in and bring-up checklist
- Boot, DDR and AXI troubleshooting
- Three-axis motion-control planning
For a sourcing request, include XC7Z020-2CLG400C, quantity, required delivery date and any lot or documentation requirements. Request a quotation. Availability, price, delivery and other commercial terms are confirmed in each written quotation.
Technical content reviewed against the linked manufacturer documents on 8 October 2026. Application calculations are planning examples, not measurements from a tested WWDParts board.