Use this XC7Z010-1CLG400I diagnostic sequence when a new board has no expected console output, an unreliable JTAG connection or failing DDR tests. Establish the earliest verified boot stage before changing components. Record observations and image revisions so that one change can be compared with the previous result; the steps below are a diagnostic plan, not claimed field measurements.
1. Start with an evidence record
Record the complete MPN, board revision, power source, rail settings, boot straps, tool version, hardware export and boot-image hash. Note whether the failure occurs on cold power-up, warm reset or both. Distinguish “no UART output” from “no JTAG connection”: they involve different initialization and visibility conditions. Use the DS187 electrical limits and UG933 board guidance for the exact rail and signal requirements.
Before powering a suspect assembly, inspect for damage and check unexpected supply shorts using the board’s expected loading. A resistance reading by itself does not identify a failed SoC. Stop testing if a measured rail violates its allowed operating conditions; repeated power cycling is not a substitute for isolating the supply fault.
2. Verify loaded power, clock and reset together
Capture the PS core VCCPINT, auxiliary VCCPAUX/VCCPLL, relevant MIO supplies and PS_POR_B over the same startup event. Measure at the device-side network where practical. VCCPINT and PL VCCINT are different supplies even when their nominal voltages match. Also check VCCBRAM, VCCAUX and PL I/O supplies for the intended debug configuration.
PS_POR_B must be held low through the mandatory supply conditions in DS187; its release timing must also meet the documented clock/reset requirements. PS_SRST_B must be inactive for boot to proceed. Verify PS_CLK frequency and signaling against its bank supply; UG933 specifies 30–60 MHz for normal operation. A clock being present does not prove that its amplitude, timing or the reset-release relationship is valid. Retain power-off and brownout captures if failures occur only on restart.
3. Decode the boot straps without reversing the bit order
Use UG585 Boot Mode Pin Settings as the source for MIO[8:2]. These pins encode more than boot-media selection. In physical pin order MIO[5], MIO[4], MIO[3], QSPI is 1,0,0 and SD is 1,1,0. Their BOOT_MODE bit ordering is different, so a register value must not be copied directly into a schematic pin sequence.
Check all seven straps, including JTAG routing, PLL bypass and MIO voltage modes. UG585 specifies 20 kΩ pull-up or pull-down straps. Verify actual populated values and external circuits that could override a level during sampling. Use the appropriate power-on reset when re-sampling straps rather than assuming a software reset applies a changed switch setting.
For a selected SD or QSPI path, check the media wiring, image location and format against the chosen boot mode and tool flow. An image that boots a development board is not automatically valid for different memory, clocks or MIO assignments. Preserve its FSBL and hardware-export identity.
4. Separate JTAG wiring from boot security and chain state
Check cable detection, target reference voltage, ground and the TCK/TMS/TDI/TDO path. The dedicated PL JTAG interface and PS peripheral-JTAG routing are different interfaces; use the exact package pin file and schematic to identify which is wired. Do not interchange PL configuration bank 0 with PS MIO bank 500 merely because both descriptions include “bank 0.”
Then check UG585 JTAG enable and control requirements. Both PS and PL power are required for the documented JTAG debug access. Cascade versus independent chain mode and security state affect visibility. A missing controller is not conclusive evidence of a solder fault. In a development configuration, a lower TCK rate can help isolate signal-integrity sensitivity; it does not qualify the final interface. Do not change security fuses as a troubleshooting experiment.
5. Locate the failed software stage
Normal boot does not promise a BootROM UART banner. Verify the UART instance, MIO routing, voltage levels and console configuration of the FSBL or application that is expected to print. If it emits nothing, use an available debugger to determine whether that code was reached rather than concluding that the BootROM is dead.
Where access permits, record UG585 BootROM error status before another reset changes the evidence. Non-secure failures can expose BOOTROM_ERROR_CODE in slcr.REBOOT_STATUS; secure failure indication has a different documented path. Interpret INIT_B only in its stated boot context, not as a generic pass/fail LED. For a controlled development test, execute a small program linked wholly into on-chip memory with appropriate PS initialization. This separates basic processor execution from DDR and the full operating system.
6. Investigate DDR failures in a reserved test environment
- Confirm the exact memory part, width, density, clock, voltage and PS DDR configuration against the fitted board. A wrong initialization file can mimic a routing fault.
- Keep the diagnostic code, stack and result log outside the memory area being overwritten. Reserve test regions; do not run destructive patterns over a live operating system.
- Log addresses, expected/actual values, bit positions, workload and temperature. Repeated byte-lane failures provide a useful correlation for layout review but do not identify the cause alone.
- Review data/strobe and address/clock groups against UG933 and the memory datasheet. Include termination, references, package delay and loaded rail behavior; do not change drive settings randomly to hide failures.
- Repeat the approved test set after each controlled change and then under the production workload. A short memory test pass is one observation, not full system qualification.
Related engineering guides
Design-in checklist · AXI and runtime diagnostics after boot
Quotation and review information
Send the complete manufacturer ordering code, quantity, required delivery date and destination in your quotation request. Include approved alternatives and any packaging, date-code or documentation requirements. Availability, price and delivery terms are confirmed in the written quotation.
Technical review: 9 October 2026. The guidance is based on the linked manufacturer documents. Planning calculations and diagnostic steps are not claims of a WWDParts-tested board or application.