This guide addresses a different stage from initial board bring-up: the XC7Z010-1CLG400I processor runs software, but access to PL registers stalls, DMA data is wrong or the system resets under load. Start by preserving the last working image and capturing the failing transaction. A successful boot does not establish that every PS–PL interface is initialized correctly.
1. Freeze the hardware and software pair
Record the loaded bitstream, hardware export, FSBL, device tree or BSP, driver and application versions. Confirm that software is addressing the register map of the image actually loaded. A correct source project does not prove that its latest bitstream is in the boot medium. Add an implementation version register to new custom IP where practical, then read it during controlled startup.
For an existing design, first check its safe identification/status registers and the documented initialization sequence. Do not probe arbitrary addresses in a running system: peripheral reads can have side effects and a transaction to an unclocked path can hang. If basic boot or DDR is not reliable yet, return to the separate startup guide.
2. Verify clocks, resets and PS–PL initialization
Confirm that PL configuration completed and that the intended PS–PL path is enabled. UG585 AXI Signals explicitly requires the PL level shifters to be enabled before communication. Review the board’s supported initialization flow instead of writing guessed register values.
Trace the actual ACLK and reset for each participating AXI interface, interconnect and peripheral. An enabled FCLK setting does not show that the signal reaches every endpoint. Likewise, a released processor reset does not show that a peripheral reset has deasserted synchronously to its clock. Use the implemented block design and observable signals to verify both ends of the path.
UG585 AXI Clocks and Resets gives a specific warning for GPV access: relevant PS–PL interface clocks must be running and resets inactive. Do not try a GPV register access as a harmless test while the path is stopped. Check clock and reset readiness before software touches that part of the system.
3. Follow the AXI transaction across boundaries
Compare the software physical address with the hardware address editor and OS mapping. Check offsets, access width and the peripheral’s allowed operation. Then observe both sides of the interconnect or clock converter with a suitably clocked ILA. The location where progress stops is more useful than the label “AXI timeout.”
| Observation | Next check | What it does not prove |
|---|---|---|
| Address request never reaches the endpoint | Address decoding, upstream enable/reset, clock conversion and software access | It does not establish that the endpoint state machine is defective. |
| Write address accepted, no response | Write-data handshake, strobes, response generation and backpressure | Address and data channels are independent; one accepted channel is not a completed write. |
| Read address accepted, no read data | Endpoint read path, reset and downstream readiness | It does not distinguish clock loss from an implementation defect without more probes. |
| DECERR or SLVERR response | Decode/protection routing or the responding component’s error condition | The response narrows the investigation; it is not proof of a single physical cause. |
Capture address, data, VALID/READY, response and reset signals over the same event. Sample each clock domain correctly; a probe clock that has stopped cannot reveal why it stopped. Review implementation timing and CDC reports alongside protocol behavior. Passing synthesis is not equivalent to passing timing or CDC review.
4. Diagnose DMA corruption through ownership and coherency
First check source/destination addresses, transfer length, alignment, stride and the buffer boundary. Preserve the DMA status before reset. Verify who owns each buffer at submission and completion, and whether the CPU or another DMA can overwrite it early. Include descriptor storage in the same investigation.
A transfer over an HP port is not automatically coherent with cached CPU data. Use the platform’s DMA mapping/synchronization API or the documented bare-metal cache maintenance. Avoid arbitrary cache-disable workarounds that hide an ownership error. UG585 PL DMA via AXI ACP explains the coherent-access option and its tradeoffs; correct transaction attributes and system setup are still required.
Use known patterns and sequence numbers to distinguish stale data, reordered frames and partial writes. For streaming input, log overflow and dropped-frame events. If a producer cannot pause, a deeper FIFO only absorbs a bounded stall; it cannot solve a sustained consumer rate lower than the producer rate.
5. Separate resets, rail events and software faults
Capture UG585 Reset Reason as early as practical. slcr.REBOOT_STATUS retains information across non-POR resets but is cleared by a power-on reset. Preserve the relevant watchdog and error logs before a recovery routine overwrites them. A watchdog reset identifies the reset mechanism, not the original reason software stopped making progress.
Correlate the failure timestamp with loaded rail voltage, resets, clock status and the workload. Use DS187 operating limits; VCCINT is PL core and VCCPINT is PS core. Measure DC accuracy and transient behavior at appropriate board points. Do not attribute every load-dependent crash to PDN weakness: memory errors, races, driver faults and thermal limits remain candidates until observations distinguish them.
Test CPU, memory and PL workloads separately before combining them. Keep a change log and reproduce the same stimulus after each adjustment. Check junction temperature against the industrial limit using a validated measurement method; a thermal-camera view of the package is not the silicon junction temperature.
6. Define the recovery and acceptance tests
- Exercise repeated driver open/close, DMA stop/start and orderly peripheral reset without discarding outstanding transactions.
- Test timeout handling and preserve diagnostic state; a CPU timeout cannot necessarily cancel an already stalled bus access. Design recovery at the affected system boundary.
- Check cold boot and non-POR restart separately with the released image pair.
- Run sustained transfers with integrity counters, buffer rollover, peak workload and the intended temperature range. Record the actual pass criteria and duration.
- Retain before/after traces, implemented timing reports and image hashes. Remove debug logic only after checking that the production build still meets timing and the same acceptance tests.
Related engineering guides
Boot, JTAG and DDR troubleshooting · Vision traffic and buffer planning
Quotation and review information
Send the complete manufacturer ordering code, quantity, required delivery date and destination in your quotation request. Include approved alternatives and any packaging, date-code or documentation requirements. Availability, price and delivery terms are confirmed in the written quotation.
Technical review: 9 October 2026. The guidance is based on the linked manufacturer documents. Planning calculations and diagnostic steps are not claims of a WWDParts-tested board or application.