Bring XC7Z010-1CLG400I into a board design by closing five decisions before layout: resource fit, pin allocation, power and reset behavior, external memory, and the boot/debug path. This guide turns those decisions into review outputs. It applies to the industrial, −1 speed-grade part in CLG400; an evaluation board preset is useful only after its differences from your board have been identified.
1. Establish the resource and clock budget
The Z-7010 provides 17,600 LUTs, 35,200 flip-flops, 80 DSP slices and 60 blocks of 36 Kb RAM, summarized as 2.1 Mb in DS190 Tables 1–2. The 28K logic-cell label is not a LUT count. BRAM is neither 240 Kb nor 150 blocks of 18 Kb. Reserve resources for interfaces, clock crossings and debug before deciding what remains for acceleration.
For −1I, DS187 Table 17 specifies a CPU limit of 667 MHz in the 6:2:1 clock ratio and 533 MHz in 4:2:1. These are conditional clock limits, not software throughput measurements or PL timing guarantees. Implement a representative datapath for the exact part, review timing and utilization, and profile the software workload before selecting a larger device.
2. Allocate interfaces before assigning the footprint
CLG400 is a 400-ball, 17 × 17 mm, 0.8 mm pitch wire-bond chip-scale BGA. The XC7Z010 version exposes 100 PL HR I/O pins; package ball count is not usable GPIO count. UG865 device pin files and Figure 4-2 are the footprint and symbol references. There is no central exposed thermal land to add beneath this BGA.
| Review item | Decision to record | Check before layout |
|---|---|---|
| PS peripherals | Controller instance, MIO route and external PHY/translator | Resolve shared MIO assignments, including debug and boot signals. |
| PL interfaces | Required pins, bank voltage, I/O standard and clock pins | Count HR pins and check each standard against the bank supply. |
| Expansion | Pins and resources reserved for later revisions | Do not assume family-wide transceiver capability: Z-7010 has no GTP/GTX. |
Keep PS MIO and PL I/O bank names separate. EMIO routes supported PS signals through PL resources; it does not add more hard peripheral controllers. A USB or Ethernet controller is not a complete connector interface: choose the required external PHY and verify the electrical interface and routing.
3. Build a rail and reset worksheet
Use DS187 Table 2 and power sequencing sections to list every supply, nominal voltage, allowed range, load estimate and enable/reset relationship. VCCPINT is the PS core supply; VCCINT is the PL core supply. VCCPAUX and VCCPLL belong to the PS, while VCCAUX and VCCBRAM serve PL functions. UltraScale+ names such as VCC_PSINTFP are not the Zynq-7000 rail names.
The recommended PS order begins with VCCPINT, then VCCPAUX/VCCPLL, then PS I/O supplies. The PL has its own recommended sequence and permitted shared-rail ramps. Distinguish recommendations from mandatory reliability conditions. PS_POR_B must remain low until VCCPINT, VCCPAUX and VCCO_MIO0 reach their specified minimum operating levels; also implement the documented power-off conditions. A PMIC does not guarantee compliance unless its configuration and actual loaded ramps satisfy these requirements.
For each rail, record startup demand and operating transients, regulator tolerance, board voltage drop and the measurement point. Choose decoupling from UG933 PDN guidance and the actual stackup. A fixed four-capacitor recipe per ball or a mandatory microvia/layer count is not a completed layout rule.
4. Select memory and derive routing constraints
Choose the exact external memory organization, voltage and timing before configuring the PS DDR controller. The PS supports DDR3, DDR3L, DDR2 and LPDDR2, subject to the device and interface constraints. A small diagnostic program can execute from on-chip memory; a Linux system needs an appropriately sized external memory design. Do not confuse the PS DDR controller setup with a separate MIG controller instantiated in PL.
Use UG933 to separate data-byte, strobe, clock and command/address routing requirements. Include package delay where the method requires it, the chosen topology, termination and the memory vendor timing. Record permitted lengths and skew by signal group. “Match every signal to the clock within five mils” is not a general Zynq rule. Have the fabricator confirm that the stackup and BGA escape can meet the resulting constraints before committing layer count.
5. Make boot and debug observable
Provide a PS_CLK source meeting the clock specification and the VCCO_MIO0 signaling level; UG933 gives a normal 30–60 MHz input range. Design accessible reset, boot-mode and JTAG connections. UG585 boot-mode settings separates the boot-device bits from JTAG-chain, PLL-bypass and MIO-voltage selections within MIO[8:2]. Copy the complete mapping into the schematic checklist instead of treating these seven pins as one binary boot-device field.
For a master boot path, BootROM starts the selected boot flow and loads the initial user code into on-chip memory, subject to the documented mode. The FSBL initializes the configured system and loads later partitions; loading PL is conditional on the image contents and application. Keep the hardware export, FSBL, bitstream, boot image and software configuration under one revision record. Verify boot-media compatibility and image layout for the selected tool release.
6. Release the design in stages
- Check unpowered assembly, then capture loaded rail ramps and reset timing before attempting a full application.
- Establish JTAG access and run a small on-chip-memory diagnostic before depending on DDR.
- Validate DDR using reserved test regions and the exact board configuration; preserve logs and failing addresses.
- Add PL and interfaces individually, then test their combined load, restart behavior and timing.
- Estimate thermal behavior using design power and the actual enclosure; verify junction temperature against the −40°C to +100°C industrial operating range. Ambient rating alone does not establish junction margin.
Related engineering guides
Specifications and pin allocation · Startup and DDR diagnostics · AXI and runtime diagnostics
Quotation and review information
Send the complete manufacturer ordering code, quantity, required delivery date and destination in your quotation request. Include approved alternatives and any packaging, date-code or documentation requirements. Availability, price and delivery terms are confirmed in the written quotation.
Technical review: 9 October 2026. The guidance is based on the linked manufacturer documents. Planning calculations and diagnostic steps are not claims of a WWDParts-tested board or application.