When a board using LCMXO2-1200HC-4TG144C does not program or start as expected, separate power, programming access, configuration and user-logic behavior. The sequence below is a document-based troubleshooting workflow, not a claim that a particular board has been tested.
HC power connection: use a nominal 2.5 V or 3.3 V external VCC supply. HC contains an internal regulator; HE and ZE use a 1.2 V external VCC supply. Do not substitute the internal core voltage for the HC board supply. See the power-supply table in the Hardware Checklist.
Start with the symptom, then run one controlled test
Use the table to choose the next test. Keep the same programming file and board revision while testing one possible cause. Save the initial log before erasing or changing configuration preferences; otherwise an apparent recovery may hide the original cause.
| Observed symptom | Next check | What the result establishes |
|---|---|---|
| The programmer cannot find its cable | Check the host cable selection, driver, USB connection and software installation before probing FPGA signals. | This is a host-to-cable problem until the cable is recognized; it does not identify a failed FPGA. |
| The cable is found, but the chain is empty or unstable | Verify VCC/VCCIO0 and the header-to-device TCK, TMS, TDI, TDO paths. Check the scan at a lower supported TCK setting. | A rate-dependent result points to a timing or connection investigation, not proof that a particular resistor fixes it. |
| The device is detected, but program or verify fails | Compare the detected target, selected operation, file, protection settings and complete first-failure log. | Detection and successful programming are separate milestones. |
| The test works until power is removed | Check whether the operation loaded volatile SRAM or programmed nonvolatile configuration Flash, and which image the boot settings select. | A successful temporary load alone does not establish persistent boot. |
| Configuration succeeds, but outputs are wrong | Check pin constraints, bank voltage, clock arrival, reset release and the first failing user-logic signal. | Continue with the implemented design and board interface rather than repeatedly erasing the device. |
Power checks: static voltage is only the first result
- Mark the actual VCC and VCCIO0 measurement points on the schematic. Note regulator settings and any series filters. Measure at the device-side points, not only at the power connector.
- For this HC part, verify the nominal 2.5 V or 3.3 V external VCC. The data sheet gives a 2.375–3.6 V recommended VCC range for the 2.5/3.3 V devices; apply the narrower requirements of each selected I/O standard to its VCCIO bank.
- Capture VCC and VCCIO0 during a failing start. Look for a stalled ramp, collapse or restart that a steady-state multimeter reading would miss. Compare the capture against the applicable power-up specifications; record time base, probe point and input conditions.
- Repeat the failing sequence consistently: cold start, warm restart or host reset. Do not change all three conditions at once. If a connected device remains powered, inspect the possibility of an input holding a rail up during shutdown.
Lattice identifies VCC and VCCIO0 as the supplies involved in internal power-good. Its checklist does not mandate a fixed rail order, but requires valid, stable supplies and discusses monotonic startup. Check Hardware Checklist sections 2, 5 and 14 and the data-sheet operating conditions. POR thresholds are not target operating voltages.
JTAG: separate a missing device from a disabled port
- Record the chain order from the schematic and compare it with the scan. Check connector orientation and continuity with power removed; then observe activity at the FPGA pins during a scan. A clock at the header alone does not prove it reaches the device.
- Confirm the programmer reference is compatible with VCCIO0 and that the grounds are connected. Use the manufacturer connection diagram, including its TCK bias recommendation. Do not add a fictional VCCJ supply or copy a header from another FPGA family.
- If access disappears after a particular image starts, inspect that image's JTAG_PORT preference. When JTAG is multiplexed with user I/O, JTAGENB and attached circuitry matter. Check for contention before enabling the port or changing an external pull resistor.
- Rescan without programming. Preserve the reported device identity and full log. Chain identification does not confirm the package, speed or temperature suffix; establish those from the fitted component and project target.
The Programming Guide, section 5.14.4 and JTAG_PORT preferences, distinguishes the default enabled port from the multiplexed mode. If the board cannot provide the required access state, stop changing software settings and review the actual schematic connection.
INITN and DONE: interpret the transition, not one voltage
First establish that the pins are enabled as configuration signals. INITN and DONE can otherwise be user I/O; a high level is not proof of successful configuration. During IEEE 1532 JTAG SRAM configuration, DONE is affected by boundary-scan behavior and is not a programming-progress indicator. Use the programmer result for that operation.
- Capture the relevant configuration signals from the start of the operation. If enabled INITN remains low, inspect initialization and any external driver holding it low.
- If INITN releases and then asserts again while configuration data is being loaded, preserve the programming/status error before retrying. Check the selected image and source rather than assuming a power fault from this signal alone.
- After a successful program-and-verify, perform the intended refresh or restart only when the controlled loads can tolerate reconfiguration. Verify the expected boot path and then test a defined user-logic output.
These distinctions follow Programming Guide sections 5.2–5.6 and the INITN/DONE descriptions. No waveform or successful board test is asserted here. The diagnostic result is the combination of your measurements, target/file identity and operation log.
Information to retain for technical support
| Item | Specification or design check |
|---|---|
| Board and component | Schematic revision, complete ordering code and package marking |
| Power | VCC/VCCIO measurements and startup captures |
| Programming | Cable, software version, selected target and full log |
| Design | Programming-file identifier, pin map and timing report |
| Failure | Reproduction steps, affected signals and captured waveforms |
LCMXO2-1200HC-4TG144C has 1,280 LUT4s and up to 107 user I/Os in the 144-pin TQFP family-table entry. HC identifies the supply/performance variant, not a high-I/O-count option. See the manufacturer selection table.
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Manufacturer documents
- FPGA-DS-02056-4.7, July 2026 — Device selection tables, 3.2 Recommended Operating Conditions, 3.5 Programming/Erase Specifications, Ordering Information
- FPGA-TN-02154-2.2 — 2 Power Supplies, 3 Power Supply Filtering, 6 Programming, 10 True-LVDS Output Pin Assignments
- FPGA-TN-02155-5.0 — 5 Configuration Process, 6 Configuration Ports, 7 Preferences
- MachXO2 family table — Device Selection Guide, 144-pin TQFP I/O count