LCMXO2-7000HC-4TG144C can be evaluated for programmable board control, interface bridging and I/O expansion. The selection decision should begin with power, pin allocation and timing constraints, before comparing logic capacity or availability.
HC power connection: use a nominal 2.5 V or 3.3 V external VCC supply. HC contains an internal regulator; HE and ZE use a 1.2 V external VCC supply. Do not substitute the internal core voltage for the HC board supply. See the power-supply table in the Hardware Checklist.
Device resources
| Item | Specification or design check |
|---|---|
| Logic capacity | 6,864 LUT4s |
| Embedded block RAM / user flash | 240 kbits / 256 kbits |
| PLLs | 2 |
| Package / maximum user I/O | 144-pin TQFP / 114; available user pins depend on enabled functions |
| External VCC | 2.5 V or 3.3 V nominal (HC) |
| Commercial junction temperature | 0°C to +85°C |
| Speed grade | -4; use timing analysis for the exact target |
Resource and package figures: Lattice device-selection table. Electrical limits and temperature: family data sheet. VCCIO must meet the selected I/O-standard limits; it is not interchangeable with VCC.
Step 1 — make a pin and startup-state worksheet
Before PCB routing, create one row for every external signal: logical name, physical package pin, I/O bank, connected device, direction, I/O standard, required startup level and whether the signal is a clock or configuration function. Include unconnected package power pins in the power review rather than treating them as spare GPIO.
Import the intended pin assignments into the project for LCMXO2-7000HC-4TG144C. Reserve the programming interface and any configuration-status functions before counting available GPIO. Keep the pin report beside the schematic so that a package or density change cannot silently reuse an old constraint file. Review dedicated clock and true-LVDS placement against Hardware Checklist sections 9, 10 and 13.
Exit check: every external connection has a physical assignment and bank voltage; no required programming or clock function depends on an assumed interchangeable GPIO.
Step 2 — define the power budget and what happens before configuration
- Specify nominal 2.5 V or 3.3 V external VCC for HC. The data-sheet recommended range is 2.375–3.6 V for these devices. Select VCCIO for each bank using the relevant I/O-standard limits, not that broad VCC range.
- Budget startup, configuration and operating current separately. Use the implemented project's power estimate with explicit activity and loading assumptions; do not size the regulator from an unrelated typical-current value.
- Review the manufacturer filtering groups against the actual package and regulator network. Check capacitor placement and current-return paths without turning one reference-board layout into a fixed layer-count requirement.
- Define how downstream enables, resets and bus drivers stay in acceptable states before user logic starts and during reconfiguration. For example, a power-enable output needs a system-level inactive state while its controlling logic is unavailable; validate the actual polarity and external circuit.
The family requires no fixed power-up rail sequence in the hardware checklist, but that does not remove supply-quality, ramp or attached-device requirements. VCC and VCCIO0 participate in internal power-good. References: Hardware Checklist sections 2–5 and data-sheet recommended operating conditions and sysIO tables.
Exit check: a rail worksheet records nominal/minimum/maximum values, regulator margin, expected loads, measurement points and startup behavior for each critical output.
Step 3 — decide how the assembly is programmed and recovered
Choose the normal programming interface, the intended configuration source and a recovery route. Document these in the project and on the manufacturing drawing. Make the interface accessible on the assembled board, including its ground and appropriate voltage reference.
- For JTAG, trace TCK, TMS, TDI and TDO from the connector through any chain to the package. Review external bias and cable-reference connections against the Lattice diagram.
- Decide whether JTAG remains enabled in user mode. If the pins are shared, review JTAG_PORT/JTAGENB behavior and prevent the other attached circuitry from driving the same pins during programming.
- Decide whether INITN and DONE are required as external status signals and set their configuration preferences accordingly. Route and pull them according to their configured function.
- Write down the selected programmer operation: SRAM load for a temporary diagnostic image, or the intended nonvolatile programming sequence for normal boot. Keep protection and Feature Row settings with the build.
The active configuration is held in SRAM; configuration Flash provides nonvolatile storage. A successful SRAM download is therefore not sufficient acceptance for power-on boot. Use the Programming Guide's configuration process, JTAG port and preferences sections when defining both operations.
Exit check: another engineer can identify the connector, reference voltage, chain order, required access state, intended operation and recovery procedure from the project records.
Step 4 — compile a small, observable bring-up image
Start with the minimum logic needed to observe the board's clock, reset and one noncritical output. Select the exact device, package and speed grade; add clock and I/O constraints before interpreting timing results. Use the utilization, pin and timing reports to check the design rather than assuming that the family resource total guarantees fit.
Choose an observable output that cannot accidentally enable a load or contend with another driver. Define the expected observation from the HDL and actual input clock. A visible toggle can help demonstrate that one path works, but it does not prove all I/O standards, PLL behavior or timing paths are correct. Expand the test one interface at a time.
Exit check: the build has a traceable source revision, exact target, pin report, clock constraints, timing results and programming-file identifier. Any unconstrained paths are reviewed before performance claims are made.
Step 5 — run the first-board acceptance sequence
| Sequence | Evidence to retain | Decision before continuing |
|---|---|---|
| Inspect unpowered connections and assembly | Schematic/PCB revision, package orientation and continuity checks | Resolve a short or assignment mismatch before programming. |
| Apply power and observe the rails | Device-side VCC/VCCIO measurements and startup captures | Compare with operating and ramp limits; a steady reading alone is insufficient. |
| Recognize the cable and scan the JTAG chain | Software/cable settings, detected device and chain order | Separate host/cable discovery from device identification. |
| Load the diagnostic image and verify the operation | File identifier, exact operation and full programmer log | Investigate the first failure before changing hardware and software together. |
| Program the intended boot image and restart | Nonvolatile operation result, boot settings and startup observation | Check that the image survives the actual power-cycle sequence. |
| Enable each application interface | Clock/reset observations, interface captures and timing constraints | Close one interface's acceptance criteria before adding another. |
If enabled configuration status is used, correlate it with the selected operation. In particular, DONE during JTAG SRAM configuration is not a standalone progress indicator. After configuration, verify the expected user function as well as the programmer result. The sequence above is a suggested engineering acceptance workflow; it is not a claim that this board or a reference design has been tested.
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Manufacturer documents
- FPGA-DS-02056-4.7, July 2026 — Device selection tables, 3.2 Recommended Operating Conditions, 3.5 Programming/Erase Specifications, Ordering Information
- FPGA-TN-02154-2.2 — 2 Power Supplies, 3 Power Supply Filtering, 6 Programming, 10 True-LVDS Output Pin Assignments
- FPGA-TN-02155-5.0 — 5 Configuration Process, 6 Configuration Ports, 7 Preferences
- MachXO2 family table — Device Selection Guide, 144-pin TQFP I/O count