XC7Z020-2CLG400C Application Guide (Xilinx Zynq-7000)

This application note outlines a three-axis step/direction controller using XC7Z020-2CLG400C. It is a planning example for separating command software from timed outputs, not a validated CNC controller, motor-driver schematic or machine-safety design.

Partition the functions before writing HDL

Putting a function in PL does not by itself make it jitter-free, fault-tolerant or safety-rated. Define timing and fault requirements first. Keep motion disabled during boot, reconfiguration and diagnostic tests until the machine’s approved conditions permit operation.

Build a numeric timing budget

As an illustrative calculation, suppose a selected driver requires 20,000 step pulses per second per axis. The commanded period is 1 / 20,000 = 50 microseconds. With an assumed 100 MHz PL timebase, that period is 5,000 clock ticks. These are example design inputs; 100 MHz must be implemented and timing-closed, and the real driver’s minimum pulse width and direction timing still govern.

Budget all three axes, acceleration profiles and coordinated updates. A software loop that occasionally meets 50 microseconds is not proof of a bounded worst-case interval. Conversely, a PL pulse generator can still produce an incorrect trajectory if software supplies incorrect or late commands.

If a queue consumes one segment every 1 millisecond and software may be delayed for 20 milliseconds, covering that assumed gap requires at least 20 queued segments before adding margin. Record how the delay bound is established. Specify the machine-approved action for an empty queue rather than allowing stale motion commands to repeat.

Check the exact package against the I/O plan

The CLG400 option provides 125 PL HR I/O, not 200, and its body is 17 × 17 mm. Assign signals by bank, voltage standard and pin capability. Step/direction outputs and encoder inputs may need external line drivers, receivers, isolation or protection chosen for the actual cable and equipment. Do not connect a field signal directly merely because spare FPGA pins exist.

Device resources include 220 DSP slices and 140 × 36 Kb block RAM blocks. Whether the proposed motion logic fits is established by synthesis and implementation, not by assuming these counts guarantee a number of axes or a control rate. The -2 CPU clock limit is mode-dependent; software execution time must be measured for the selected configuration.

Manufacturer references: DS190: Zynq-7000 SoC overview, Tables 1–2; DS187: Z-7020 electrical and switching specifications, Tables 2, 17 and power/reset requirements; UG865: packaging, pinout and mechanical drawings.

Define the PS-to-PL command contract

• Use versioned control/status registers with documented widths, units, valid ranges and reset values.
• Define how a multi-axis command becomes active together; avoid partially updated commands crossing a software write sequence.
• Include sequence identifiers, queue occupancy and fault status so software can distinguish accepted, running and completed work.
• Specify synchronization between the AXI control clock, motion timebase and external inputs. Treat unrelated inputs as clock-domain crossings.
• For bulk buffered commands, define DMA ownership and completion before reusing memory. A completed bus transfer is not the same event as completion of the commanded motion.

Power, memory and boot preparation

Follow the separate PS/PL supply and reset requirements in DS187 and use the actual memory part when generating PS configuration. BootROM and FSBL have different roles: the usual flow loads FSBL into on-chip memory, then initializes the system and loads subsequent software and an optional PL bitstream. Ensure outputs remain in the intended inactive state throughout that process.

Develop software and PL against one versioned hardware definition. If Linux is used for command preparation, account for scheduling and competing I/O; do not assume that assigning another core automatically establishes a hard real-time bound. Review the board design-in checklist for DDR, PDN, package and thermal work rather than copying a fixed layer count or an invented exposed-pad footprint.

Manufacturer references: DS187: Z-7020 electrical and switching specifications, Tables 2, 17 and power/reset requirements; UG1283: Zynq-7000 boot and configuration.

A staged verification plan

1. Begin with a simulation of pulse width, direction changes, coordinated start and arithmetic limits using the selected driver’s requirements.
2. On hardware, validate counters and command handling with outputs disconnected from machinery or otherwise in the approved safe test state. Capture timing rather than relying on a software status flag.
3. Exercise minimum/maximum commanded rates and acceleration transitions; compare requested and observed pulse counts on all axes.
4. Test queue underrun, invalid commands, reset and communication interruption in the approved test environment. Verify the specified fault behavior and the independent machine-safety system through its own acceptance process.
5. Add representative UI, network and storage load; log queue occupancy and timing. Confirm supply/temperature margin under the combined workload.
6. Freeze the accepted hardware, software, tool and parameter versions before production use.

Continue your design review

• Device specifications and ordering checks
• Board design-in and bring-up checklist
• Boot, DDR and AXI troubleshooting
• Machine-vision bandwidth planning

For a sourcing request, include XC7Z020-2CLG400C, quantity, required delivery date and any lot or documentation requirements. Request a quotation. Availability, price, delivery and other commercial terms are confirmed in each written quotation.

Technical content reviewed against the linked manufacturer documents on 8 October 2026. Application calculations are planning examples, not measurements from a tested WWDParts board.