A data-acquisition design using XC7K325T-1FFG900C needs a budget for the entire path from converter to host. FPGA resources are only one part of that budget: sample formatting, clock crossings, memory traffic and host stalls often determine whether data is preserved. The example below describes a hypothetical eight-channel acquisition system. Its numbers are planning calculations, not a tested reference design or a promised performance level.
Define the sample contract before choosing interfaces
Assume eight channels, 16 bits per sample and 40 million samples per second per channel. Raw payload is 8 × 16 × 40,000,000 = 5.12 Gb/s, or 640 MB/s using decimal megabytes. A timestamp, channel identifier, packet header or alignment padding increases the transport rate. Record whether the application transfers raw ADC codes, sign-extended values or processed results; those formats can require different bandwidth.
A source-synchronous LVDS converter interface uses the appropriate SelectIO resources and clocking, whereas a JESD serial interface uses transceivers and its associated protocol implementation. They are not interchangeable names for the same pins. Select the actual converter and interface mode first, then assign clock and data resources. A family transceiver headline cannot establish support for every ADC protocol configuration.
Keep a stage-by-stage bandwidth worksheet
| Converter payload | 640 MB/s under the stated eight-channel assumptions |
|---|---|
| After decimation by four | 160 MB/s if each retained sample remains 16 bits |
| If processed samples expand to 32 bits | 320 MB/s after that same decimation |
| 512 KiB input buffer | About 0.8192 ms at 640 MB/s before overhead |
| Illustrative 64-bit DDR at 800 MT/s | 6.4 GB/s raw bus transfer rate, not application throughput |
| PCIe Gen2 x8 arithmetic | 4 GB/s per direction after 8b/10b coding, before transaction and system overhead |
These are deliberately different quantities. The DDR figure is a bus calculation, while the input figure is useful sample payload. A sustained-rate comparison must subtract refresh, arbitration, command overhead and the traffic caused by writing and rereading the same samples. Similarly, PCIe lane capacity is not an end-to-end DMA benchmark.
Allocate block RAM for latency, not just capacity
XC7K325T provides 445 physical 36 Kb block-RAM resources. AMD DS180: 7 Series FPGAs Overview. For an illustrative input FIFO, allocate 128 blocks in a 32-data-bit by 1,024-word organization. Payload capacity is 128 × 4 × 1,024 = 524,288 bytes, or 512 KiB. At 640,000,000 bytes/s it stores 0.0008192 seconds of data, approximately 0.8192 ms.
That is a small tolerance for a host or memory stall. If a non-pausable source can be blocked for 5 ms, the raw stream alone needs 3,200,000 bytes of buffering, before margin. This exceeds the example on-chip allocation and calls for a different buffering plan, reduced input rate, or explicit loss behavior. Do not promise lossless capture merely because the average output bandwidth exceeds the average input bandwidth.
Define overflow behavior during architecture review. Options include stopping the acquisition, dropping complete frames with a recorded gap, or overwriting older data in a bounded history buffer. Each has different measurement consequences. Silent truncation is especially difficult to diagnose because file size can look plausible while sample continuity has been lost.
Budget memory-controller traffic and backpressure
The external-memory solution must be generated for the actual FPGA, speed grade and design frequency; AMD UG586: Memory Interface Design Rules documents those selection constraints. The AMD UG586: Memory Controller and Native Interface describes the controller/native interface and scheduling. Treat the generated core’s ready/valid behavior as part of the data-path contract.
In the hypothetical 64-bit, 800 MT/s example, the raw calculation is 8 bytes × 800 million transfers/s = 6.4 GB/s. Writing 640 MB/s and later reading it once creates 1.28 GB/s of payload traffic before other clients and overhead. The apparent difference between 1.28 and 6.4 is not a guaranteed margin: short bursts, direction changes and competing accesses can lower delivered throughput.
Test the memory subsystem first with synthetic patterns and an error counter. Then replay the intended burst lengths and read/write ratio. Capture maximum service latency as well as average throughput. A FIFO sized only from the average may overflow during a refresh or host-stall episode even while the long-term bandwidth number appears adequate.
Separate DSP arithmetic from placement feasibility
Suppose each of the eight channels runs a 32-tap FIR at 40 MSPS. A direct calculation gives 8 × 32 × 40 million = 10.24 billion multiply-accumulates per second. If a proposed implementation can sustain one such operation per DSP per 200 MHz clock, the arithmetic lower bound is ceil(10.24 billion / 200 million) = 52 DSPs. This is an assumed mapping and clock rate, not a completed implementation.
Coefficient width, sample width, symmetry, rounding, saturation and pipeline design can alter the mapping. Time sharing also adds control and storage requirements. Check the synthesized resource count and post-route timing, then verify numerical behavior with worst-case input vectors. A low nominal DSP utilization does not prove that routing or clock-crossing requirements are satisfied.
Allocate GTX lanes and transport overhead explicitly
FFG900 bonds out 16 GTX channels, while the exact -1 part’s listed line-rate ceiling is 8.0 Gb/s rather than the family’s 12.5 Gb/s headline. AMD DS180: 7 Series FPGAs Overview and AMD DS182: Kintex-7 DC and AC Switching Characteristics. AMD PG054: Available PCIe Integrated Blocks identifies the PCIe block availability. Reserve the actual lanes and reference-clock connections used by every interface before assuming the remaining channels are freely interchangeable.
For PCIe Gen2 x8, 8 lanes × 5 GT/s × 8/10 / 8 gives 4 GB/s in each direction before packet overhead. Host memory, DMA descriptors, interrupt behavior and software buffering further affect useful throughput. Measure the complete capture-to-file path with the intended host and storage system; a link-training success alone establishes none of those sustained-rate results.
A practical acquisition acceptance test
- Generate a deterministic sample sequence with channel identifiers and monotonically increasing counters; verify continuity after every buffer boundary.
- Inject a bounded host pause and check FIFO high-water marks against the predicted byte budget. Confirm the documented overflow response when the pause exceeds capacity.
- Reset one clock domain or interface while the others remain active. Ensure restart creates an explicit acquisition boundary rather than silently mixing old and new samples.
- Repeat at the intended channel count, word format and processing mode. Log dropped frames, memory errors and transport retries separately.
- Preserve tool version, bitstream hash, timing results, temperature conditions and host configuration with the test record.
Use the part specification guide to review package and ordering constraints. If the board does not reach stable capture, follow the power, configuration and link troubleshooting workflow before changing the system budget.
Ordering and references
For an XC7K325T-1FFG900C quotation, send the complete code, quantity, required delivery date and documentation requirements through the WWDParts RFQ list. Availability, price and delivery terms are confirmed in the written quotation. A different package, temperature grade or speed grade requires a design review before substitution.
- AMD DS180: 7 Series FPGAs Overview
- AMD DS182: Kintex-7 DC and AC Switching Characteristics
- AMD UG586: Memory Interface Design Rules
- AMD UG586: Memory Controller and Native Interface
- AMD PG054: Available PCIe Integrated Blocks
Technical content reviewed October 13, 2026. Worked examples are design calculations with stated assumptions, not measurements or hardware qualification results.