Debug an XC7A35T-1CPG236C board by separating power, configuration, application logic and external interfaces. Record measurements before changing the design. A low DONE signal, missing JTAG device or failed serial link is an observation, not proof of a damaged or counterfeit FPGA. This guide is based on AMD documentation and does not claim personal field-test experience.
Start with a repeatable test configuration
Record the board revision, exact FPGA marking, programming cable, tool version and bitstream build. Keep a minimal test image for the actual device and board. Use the same supply conditions and reset sequence for each comparison. Confirm the intended measurement point in the schematic rather than assuming a nearby capacitor belongs to the rail of interest.
Power and JTAG checks
Check VCCINT, VCCBRAM, VCCAUX and each required VCCO rail at accessible points near the FPGA. Capture ramp-up and loaded behavior with appropriate probing. For this -1 device, VCCINT and VCCBRAM are nominally 1.0 V and VCCAUX is nominally 1.8 V. Include the transceiver and analog supply connections specified for the design.
DS181: operating conditions and sequencing describes the recommended sequence VCCINT, VCCBRAM, VCCAUX, VCCO, including permitted simultaneous ramps and additional 3.3 V bank conditions. A missing VCCBRAM or incorrect configuration-bank voltage can be overlooked by a simplified three-rail checklist.
For an undetected JTAG chain, inspect cable ground, target-reference voltage, TCK, TMS, TDI and TDO connections, chain order and continuity. The JTAG interface uses bank 0 at VCCO_0 voltage, as described in UG470: configuration and device ID codes. Checking VCCAUX alone is insufficient. Confirm CFGBVS against the configuration-bank voltage; never change a pull-up to a convenient rail without checking that relationship.
Lowering TCK can help identify a marginal chain, but successful detection at a lower frequency is not a complete signal-integrity diagnosis. Compare against a known working cable or board where possible, and record the changed condition.
Interpret INIT_B and DONE correctly
| Observation | Next checks |
|---|---|
| INIT_B low during reset/initialization | This is expected during configuration-memory clearing. Check when it releases relative to rails and PROGRAM_B. |
| INIT_B becomes low during configuration | Investigate a configuration error, including data/CRC conditions; it does not go high to signal a CRC error. |
| DONE remains low | Read status and examine the startup/configuration sequence. Check bitstream selection, straps, clocking and the external source. |
| JTAG configuration works, SPI boot fails | Focus on the boot source, mode, flash contents and interface; also investigate cold-start timing and supply differences. |
| DONE high but application inactive | Check user clocks, resets, constraints and application readiness independently. |
Master SPI generates its configuration clock through CCLK. JTAG configuration uses TCK. A missing user oscillator is not a universal explanation for failed JTAG configuration. When examining SPI boot, decode the transactions and compare the read command, addressing, bus width and clock rate with the selected flash data sheet.
I/O works intermittently
Compare each XDC pin assignment with the board net and bank. Verify the I/O standard, bank voltage, drive strength, slew and termination against the receiver requirements. Check for output contention and voltage overshoot before attributing heat or errors to the device itself.
CPG236 uses HR user-I/O banks. UG471: SelectIO resources states that HR banks do not have DCI; changing DCI_CASCADE or wiring a DCI reference is not an Artix-7 HR-bank repair. Supported differential or other termination features must be checked separately for the chosen standard.
GTP link and memory-interface faults
The CPG236 package exposes two GTP channels. For a design using them, check the selected channel pins, reference-clock routing and frequency, transceiver rails, reset sequence and PLL status. Use a generated example or PRBS test to distinguish the physical link from the application protocol. UG482: GTP transceiver architecture and debug is the relevant architecture guide. GTP uses a linear equalizer; do not import GTX/GTH DFE tuning instructions into this device.
For DDR calibration failures, first confirm that the exact part, package, memory configuration and pin plan are supported by MIG. Start from its generated example and inspect calibration status before adding application traffic. Use UG586: memory interface implementation for memory-interface rules; UG473 describes internal block RAM and is not the DDR board-routing guide. A calibration success does not prove sustained error-free transfers under every traffic and temperature condition.
Keep an evidence record
For each fault, save supply captures, programming/status logs, relevant constraints, failing traffic patterns and the results after each single change. Repeated failures on one assembly may justify assembly inspection, but a successful JTAG scan or a visual marking comparison alone does not certify the part or the board. Escalate with reproducible evidence instead of declaring the FPGA faulty from one symptom.
Sources and next steps
- DS181: operating conditions and sequencing
- UG470: configuration and device ID codes
- UG471: SelectIO resources
- UG482: GTP transceiver architecture and debug
- UG586: memory interface implementation
Review the supporting-circuit design checklist.
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Technical content reviewed against manufacturer documentation on October 12, 2026. Design examples are calculations and planning guidance, not measured performance or a qualified reference design.