XC7A35T-1CPG236C Troubleshooting Guide: Common Problems and Solutions

As an experienced hardware engineer, I know the frustration of a board-bring up that stalls. You've meticulously designed your PCB, the assembly looks clean, but the FPGA at its heart, the Xilinx XC7A35T-1CPG236C, isn't behaving as expected. This guide is a distillation of over 15 years of debugging FPGAs, focusing specifically on the common pitfalls encountered with the Artix-7 family. We'll move from power-up to configuration and I/O, providing systematic checks based on datasheet requirements and real-world field experience to get your project back on track.

XC7A35T-1CPG236C Quick Reference

Before diving into troubleshooting, let's establish a baseline of the device's key characteristics. The XC7A35T-1CPG236C is a cost-optimized FPGA from the Xilinx Artix-7 family, designed to balance performance, power, and price. It's commonly found in applications like machine vision, industrial control, software-defined radio, and advanced medical devices where significant parallel processing is needed in a compact form factor. Understanding its core resources is the first step in debugging.

Parameter	Value
FPGA Family	Artix-7
Logic Cells	33,280
LUTs	20,800
Block RAM	1,800 Kbits
Maximum User I/O	106
Package	CPG236 (12x12mm)
Speed Grade / Temp	-1 / Commercial (0°C to 85°C Junction)

Problem #1: Configuration Failure (DONE Pin Stays Low)

Symptom: After power-on or attempting to program the device, the `DONE` pin never transitions to a high state. The FPGA is not functional, and downstream devices that rely on the `DONE` signal are not enabled. Vivado Hardware Manager may report a failure to program or a timeout.

Root Cause: This is the most fundamental FPGA failure mode and almost always points to one of three areas: power, clock, or the configuration sequence itself. The FPGA has a strict power-on sequence and requires a stable clock source to load its configuration bitstream from memory (e.g., a SPI flash) or via JTAG.

Fix: Follow this systematic approach. Do not skip steps.

1. Power Rail Verification: The Artix-7 has multiple power domains. Probe each one directly at the FPGA's BGA balls (or the closest decoupling capacitor). Do not trust measurements at the power supply output.
   • VCCINT (1.0V): This is the core voltage. It must be stable and within the datasheet tolerance (typically ±5%). Ripple on this rail is a common cause of subtle, hard-to-diagnose failures.
   • VCCAUX (1.8V): Powers auxiliary internal logic, including the JTAG interface. If VCCAUX is missing or incorrect, JTAG will fail.
   • VCCO (1.2V - 3.3V): This is the I/O bank voltage. There can be multiple VCCO rails for different I/O banks. Ensure each bank you are using is powered with the correct voltage for the I/O standard you've defined in your design.
2. Power-On Sequencing: Refer to the Artix-7 FPGAs Data Sheet (DS181), specifically the "Power-On/Off Power Supply Sequencing" section. The recommended sequence is VCCINT, then VCCAUX, then VCCO. While the device has some tolerance, deviating significantly can put the internal power-on reset (POR) circuitry into an unknown state. If your power supplies ramp simultaneously, ensure they all meet the monotonic ramp requirement.
3. Configuration Mode Pins (M[2:0]): These three pins dictate how the FPGA expects to be configured (e.g., Master SPI, Slave Serial, JTAG). Check their voltage levels at the FPGA pins. They are sampled at power-up. An incorrect pull-up/pull-down resistor value or a floating pin can cause the FPGA to wait for a configuration source that isn't there. For JTAG programming, the typical mode is JTAG-only (M[2:0] = 101).
4. Control Signal Status:
   • PROGRAM_B: This pin should be high. If it's held low, the FPGA is perpetually held in a reset/clearing state. Check for shorts to ground or a faulty open-drain driver holding it down.
   • INIT_B: This is an open-drain status pin. It will go low during configuration and then release (go high via a pull-up resistor) if a CRC error or other configuration data error is detected. If INIT_B is stuck low, it's a strong indicator of a corrupt bitstream or a problem reading from the configuration flash.
5. Configuration Clock (CCLK): If using a mode like Master SPI, the FPGA generates CCLK to read the flash. Probe this pin. If there's no clock, the FPGA isn't even attempting to read. This again points back to power or mode pin issues.

Problem #2: JTAG Chain Not Detected or Unreliable

Symptom: Xilinx Vivado Hardware Manager cannot detect the XC7A35T-1CPG236C. It might show "No devices found" or an error about the JTAG chain being broken. In some cases, it may detect the device intermittently.

Root Cause: JTAG is a serial bus. Any single point of failure along the chain (TDI, TDO, TCK, TMS) will break communication for all devices in the chain. Common causes include incorrect PCB wiring, missing pull-up/pull-down resistors, poor signal integrity, or an incorrect VCCAUX voltage.

Fix: Debugging a JTAG chain requires methodical verification.

1. Confirm VCCAUX: The JTAG and other auxiliary logic are powered by VCCAUX (1.8V). Without this rail, the JTAG port is dead. Verify this voltage first.
2. Check JTAG Header and Wiring:
   • Verify the pinout of your JTAG header (e.g., Xilinx 2x7 header) matches the connections to your programming cable. A common mistake is swapping TDI and TDO.
   • TDI/TDO Chain: In a multi-device chain, the TDO of one device must connect to the TDI of the next. The first device's TDI comes from the header, and the last device's TDO goes back to the header. Ensure this daisy-chain is correctly implemented on your PCB.
   • TCK and TMS: These are broadcast to all devices in the chain in parallel.
3. Essential Resistors:
   • Pull-up on TDO, TMS, TDI: The Xilinx JTAG interface expects weak pull-ups on these lines. A value between 1kΩ and 10kΩ is typical. Check your schematic.
   • Pull-down on TCK: A weak pull-down on TCK helps prevent spurious clock edges. This is especially important.
4. Signal Integrity: JTAG is not typically high-speed, but on a noisy board, problems can arise.
   • Reduce JTAG Clock Speed: In Vivado Hardware Manager, you can often reduce the JTAG TCK frequency. Try setting it to a very low value (e.g., 1 MHz or lower). If the device is detected at a lower speed, it points to a signal integrity problem on your board (e.g., long traces, excessive noise coupling, or incorrect termination).
   • Check for Stubs: Long, unterminated traces (stubs) off the main JTAG lines can cause reflections. Keep JTAG routing clean and direct.
5. Isolate the Problem: If you have multiple devices in the JTAG chain, try to isolate the XC7A35T. If possible, use jumpers or rework the board to create a chain with only the FPGA. If that works, the problem lies with one of the other devices or the connections between them.

Problem #3: Unexpected I/O Behavior or Signal Integrity Issues

Symptom: The FPGA configures successfully (DONE is high), but interfaces connected to it are not working. This could manifest as a memory interface failing calibration, an Ethernet PHY not linking up, or simple GPIOs showing incorrect logic levels.

Root Cause: This category of problem is broad, but it often boils down to a mismatch between the logical design (HDL and constraints) and the physical reality (PCB and external components). This includes incorrect I/O standards, drive strengths, termination, or signal integrity issues on the PCB.

Fix: This requires checking both your software (Vivado project) and hardware.

1. Verify VCCO and I/O Standards: Every I/O bank on the FPGA is powered by a VCCO pin. The voltage applied to this pin *must* match the I/O standard you have defined for the pins in that bank in your XDC constraints file. For example, if you have defined an output as LVCMOS33, the corresponding VCCO bank must be powered at 3.3V. A mismatch will lead to incorrect voltage levels, potential damage to the FPGA or connected devices, and interface failure.
2. Check I/O Constraints (XDC file):
   • Pin Locations: Double-check that the pin locations in your XDC file match the schematic. A single swapped pin in a parallel bus is a common and frustrating error.
   • Drive Strength and Slew Rate: For outputs, the default drive strength and slew rate may not be appropriate. A fast slew rate on a long, unterminated trace is a recipe for ringing and overshoot. Conversely, a drive strength that is too weak may not be able to drive the capacitive load of the trace and receiver, resulting in slow rise/fall times. Experiment with `DRIVE` and `SLEW` properties in your XDC file.
3. Termination and DCI: High-speed signals require proper termination to maintain signal integrity.
   • External Termination: For standards like LVDS, ensure your 100Ω differential termination resistor is placed correctly (close to the receiver pins).
   • Digitally Controlled Impedance (DCI): Artix-7 devices support DCI, which uses internal termination to save board space. However, DCI has strict rules. It requires a reference voltage (VRP) and specific VCCO voltages. If DCI is not working, check that the `DCI_CASCADE` constraint is correct and that the VRP pin is properly connected. As a debug step, consider disabling DCI and using external termination to see if the problem is resolved.
4. Differential Pair Routing: For differential signals (like LVDS or TMDS), verify that the P and N traces are length-matched and have controlled differential impedance (typically 100Ω). Skew between the two traces can collapse the eye diagram and cause bit errors.

Systematic Debug Checklist

When a board first comes up, emotions can run high. Use a systematic, dispassionate checklist to find the root cause. This table provides a logical flow from power to full operation.

Step	Check Item	Expected Result	If Failed
1	Visual Inspection	No solder bridges, correct component orientation, no visible damage.	Rework board under microscope.
2	Power Rails (VCCINT, VCCAUX, VCCOs)	Correct, stable voltage at FPGA pins (or nearest cap). Low ripple.	Debug power supply regulators. Check for shorts.
3	Power-On Sequence	Rails ramp in the order specified by datasheet DS181 (VCCINT -> VCCAUX -> VCCO).	Adjust power supply sequencing/enables.
4	Configuration Mode Pins (M[2:0])	Correct voltage levels for intended boot mode (e.g., 101 for JTAG).	Check pull-up/pull-down resistors and values.
5	Control Pins (PROGRAM_B, INIT_B)	PROGRAM_B is high. INIT_B is high (after any config attempt).	Check drivers holding pins low. If INIT_B is low, suspect bitstream/flash.
6	JTAG Chain Detection	Vivado Hardware Manager detects the XC7A35T.	Follow JTAG debug steps (Problem #2). Check VCCAUX.
7	FPGA Configuration	`DONE` pin goes high after programming.	Follow configuration failure steps (Problem #1). Check bitstream source.
8	I/O Bank Voltages (VCCO)	VCCO voltage matches the I/O standard defined in the design for that bank.	Correct power supply or update I/O standard in XDC constraints.

This checklist covers the most frequent bring-up hurdles. If you've gone through this entire list and the device still fails, the problem may be more subtle. Consider issues like a faulty clock oscillator, signal integrity on high-speed interfaces that requires simulation, or, in rare cases, a damaged FPGA. For more complex design-specific issues, leveraging the Xilinx support forums and application notes for the Browse Artix-7 Series can provide deeper insights. Always have the official datasheets and user guides open during debug.

Sourcing and Counterfeit Avoidance

In today's strained supply chain, the temptation to source components from unauthorized, third-party brokers on platforms like eBay or AliExpress is high. For a complex device like the XC7A35T-1CPG236C, this is a significant risk. Counterfeit or improperly handled FPGAs are a major source of debug headaches that mimic real design flaws.

Common issues with non-authorized parts include:

• Remarked Devices: A lower-cost, lower-speed grade, or different temperature grade part is sanded and re-lasered to look like the more expensive XC7A35T-1CPG236C. It might fail at temperature or when running at the target clock speed.
• Recycled/Reballed Parts: Devices salvaged from e-waste, with BGA balls re-applied using an uncontrolled process. These have a high risk of solder joint failure, internal damage from improper removal, and latent ESD damage.
• Empty Shells or Wrong Dies: In the worst cases, the package may be an empty piece of plastic or contain a completely different, non-functional piece of silicon.

These fraudulent parts can cause intermittent failures, configuration problems, and excessive power consumption that will waste countless hours of engineering time. The only reliable method to avoid these issues is to source components through an authorized or highly trusted distributor that has a rigorous quality control and counterfeit detection process. A trusted supplier provides traceability back to the original component manufacturer (OCM), ensuring the part you receive is authentic and meets all datasheet specifications. Before beginning a production run, it is wise to Check XC7A35T-1CPG236C Inventory & Pricing with a reputable source to secure genuine components and avoid production delays and costly field failures.

Video Demonstration

Frequently Asked Questions (XC7A35T-1CPG236C FAQ)

Why is the DONE pin on my XC7A35T-1CPG236C stuck low after I try to program it?

A DONE pin that remains low is the classic sign of a configuration failure. The most common culprits are power supply issues (VCCINT, VCCAUX, VCCO must be stable and at the correct voltage), an incorrect configuration mode set by the M[2:0] pins, or a problem with the configuration data itself. Also, check that the PROGRAM_B pin is not being held low, and monitor the INIT_B pin; if it goes low and stays low, it often indicates a CRC error in the bitstream, meaning the file is corrupt or not being read correctly from the flash memory.

Vivado can't find my XC7A35T on the JTAG chain. What should I check first?

Start with the basics. First, confirm the VCCAUX (1.8V) rail is active and correct, as it powers the JTAG port logic. Second, verify the physical connections from your JTAG programmer to the board, ensuring TDI, TDO, TCK, and TMS are not swapped. Third, check your schematic for the required pull-up resistors on TDO, TMS, and TDI, and a pull-down on TCK, as these are critical for reliable JTAG operation.

My FPGA seems to be running hot, even with a simple design. What could be the cause?

Excessive power consumption can point to several issues. The most likely hardware cause is I/O contention, where another device on the board is driving a signal into an FPGA pin that is also configured as an output. Another possibility is a floating input pin; all unused I/O pins should be tied to a known state (GND or VCC) either externally with resistors or internally using constraints (`set_property PULLUP true [get_ports <port_name>]`). Finally, if you sourced the part from a non-authorized channel, it could be a remarked, lower-grade part that is less power-efficient.

Can I use different I/O voltages (e.g., 1.8V and 3.3V) on the same XC7A35T-1CPG236C?

Yes, this is a key feature of the Artix-7 architecture. The I/O pins are grouped into banks, and each bank has its own VCCO power supply pin. You can power one bank's VCCO at 1.8V to interface with 1.8V logic, and another bank's VCCO at 3.3V for 3.3V logic. You must ensure that all I/O standards used for pins within a specific bank are compatible with that bank's VCCO voltage, as defined in your XDC constraints file.

I've checked all power and JTAG signals, but my board still won't program. Could the FPGA be damaged?

While possible, outright device failure is less common than a design or assembly error. Before concluding the FPGA is damaged, exhaust all other possibilities. Try a different JTAG programming cable and a different PC to rule out toolchain issues. Use an oscilloscope to check for a clean, stable clock signal at the FPGA's clock input pin. If you have a second, identical board, try programming it; if the second board works, it strongly suggests a localized assembly issue (like a cold solder joint under the BGA) or a damaged component on the first board.

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