A 16-channel acquisition system at 1 million samples/s per channel places different demands on XC7A35T-1CPG236C than a slow sensor monitor. Start with the complete data path: converter timing, capture, buffering, processing and host throughput. The calculations below describe an illustrative 16-bit design; they are not measured performance or a validated reference circuit.
Calculate the payload and the stall budget
Sixteen channels × 16 bits × 1,000,000 samples/s produce 256,000,000 bit/s, or 32,000,000 bytes/s, before timestamps, framing and integrity fields. A 100 Mb/s link cannot transport that raw continuous payload. A nominally faster interface must still be evaluated by sustained application throughput rather than its headline signaling rate.
Suppose the host can stall for 10 ms. During that interval the raw samples accumulate 320,000 bytes. The FPGA's total physical block RAM is 230,400 bytes, calculated from 50 × 36 × 1,024 / 8. Even allocating every physical bit would not cover that stall, and a real design also consumes memory for FIFO organization and other functions.
The idealized all-BRAM storage time is 230,400 / 32,000,000 = 7.2 ms. Treat this as a hard arithmetic upper bound, not achievable payload depth. The design therefore needs a shorter guaranteed stall, external buffering, reduced traffic, or an explicit acquisition-stop/data-loss policy.
Choose converters by the actual conversion requirement
Specifying the AD7606 family or a generic SPI ADC is insufficient to establish 1 MSPS on every channel. Check the complete converter code, simultaneous-sampling behavior, conversion and readout timing, analog performance and electrical interface. Different devices in one family can have different limits.
A shared FPGA trigger does not by itself guarantee analog simultaneity. Account for converter aperture behavior, trigger distribution skew and each device's sampling mode. If phase alignment matters, define the permitted channel skew and a way to measure it with a common stimulus.
Allocate pins and bandwidth together
A bank of 16-bit parallel converters can exhaust the 106 user I/O of CPG236 quickly. Serial interfaces reduce data pins but increase per-lane throughput and timing demands. Make an explicit pin list including clocks, strobes, resets, host interface, configuration and any external memory. Validate bank voltages and placement before selecting a layout.
DS180: device resources and package combinations specifies the package I/O and device resources. Two GTP channels are exposed in CPG236; their existence does not make every serial protocol or line rate available. Use the exact -1 electrical limits and protocol implementation, together with UG482: GTP transceiver architecture and debug, when considering a transceiver-based uplink.
Use a staged data path
| Stage | Design question |
|---|---|
| Capture | Which edge identifies a valid sample, and how are external setup/hold requirements constrained? |
| Clock-domain crossing | Which source and destination clocks are independent, and which FIFO or handshake handles each crossing? |
| Processing | What precision, overflow policy, latency and resource use does the actual filter require? |
| Buffering | What measured host stall must be tolerated, and how is occupancy monitored? |
| Transport | What is sustained payload capacity after framing, software and protocol overhead? |
For an illustrative 32-tap FIR applied independently to all 16 channels at 1 MSPS, a straightforward implementation needs 512 million multiply-accumulate operations/s. That is an operation count, not a claim that 512 DSP blocks are needed or that the 90 DSP48E1 slices automatically meet the design. Time sharing, parallelism, coefficient structure, pipeline depth, arithmetic width and attainable clock frequency determine the implementation.
Model fixed-point ranges and compare output against a numerical reference before optimizing. Test maximum inputs and transitions, not only small sine waves. Keep saturation, rounding and dropped-frame indicators visible to the host.
External memory and host control
If external DDR memory is required, confirm the exact device/package combination and a legal pin plan in MIG before committing to the board. Use its generated example and the rules in UG586: memory interface implementation to establish a working interface. Do not presume that the full ADC bank, DDR bus and host interface all fit simultaneously because the total I/O count sounds large.
A soft processor can manage configuration and supervision, but the capture path should not depend on unspecified software response time. Define what happens during host disconnection, reset and buffer overflow. For continuous recording, sequence numbers and error counters help distinguish a valid quiet signal from missing data.
Validate the acquisition claim
- Prove the selected converters meet the required rate and sampling alignment.
- Simulate capture and arithmetic against controlled input patterns.
- Run timing and clock-domain-crossing checks on the implemented design.
- Measure sustained host traffic with the final framing and software.
- Inject the maximum specified host stall and verify the buffer policy.
- Repeat representative traffic under expected power and temperature conditions.
Only after these tests should the system be described as a working 16-channel, 1 MSPS/channel acquisition solution. The FPGA resource table is an input to that assessment, not its conclusion.
Sources and next steps
- DS180: device resources and package combinations
- DS181: operating conditions and sequencing
- UG482: GTP transceiver architecture and debug
- UG586: memory interface implementation
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Technical content reviewed against manufacturer documentation on October 12, 2026. Design examples are calculations and planning guidance, not measured performance or a qualified reference design.