LCMXO2-7000HC-4TG144C is a Lattice MachXO2 programmable logic ordering code. This overview separates its published resources from the board-specific checks needed for selection and sourcing.
HC power connection: use a nominal 2.5 V or 3.3 V external VCC supply. HC contains an internal regulator; HE and ZE use a 1.2 V external VCC supply. Do not substitute the internal core voltage for the HC board supply. See the power-supply table in the Hardware Checklist.
Specifications
| Item | Specification or design check |
|---|---|
| Logic capacity | 6,864 LUT4s |
| Embedded block RAM / user flash | 240 kbits / 256 kbits |
| PLLs | 2 |
| Package / maximum user I/O | 144-pin TQFP / 114; available user pins depend on enabled functions |
| External VCC | 2.5 V or 3.3 V nominal (HC) |
| Commercial junction temperature | 0°C to +85°C |
| Speed grade | -4; use timing analysis for the exact target |
Resource and package figures: Lattice device-selection table. Electrical limits and temperature: family data sheet. VCCIO must meet the selected I/O-standard limits; it is not interchangeable with VCC.
Supply limits and pinout
The current family data sheet lists 2.375–3.6 V for the recommended HC VCC operating range. Nominal operation is 2.5 V or 3.3 V. Do not confuse this with the 1.14–1.26 V range for the 1.2 V variants. Use the I/O-standard table separately for VCCIO. See recommended operating conditions and sysI/O limits.
Use the manufacturer package drawing and pinout for the exact ordering code when creating a schematic symbol or footprint. The package pin count includes power and configuration functions; it is not the user-I/O count. Reserve programming and clock access before allocating general-purpose signals.
Configuration and implementation
MachXO2 includes internal configuration flash. Choose the intended configuration mode and retain the generated programming file with the project's target selection and build record. A nominal boot-up description is not a substitute for checking the startup timing required by the surrounding system.
Compile the actual design before approving the part. Review pin assignments, logic and memory utilization, clocking and constrained timing. Use the manufacturer's programming-cycle specifications if the application will repeatedly update flash; do not base endurance calculations on an unsourced cycle count.
Alternative parts
Compare the complete proposed ordering code, supply architecture, pin functions and implementation results. A shared TG144 package or a different speed/temperature suffix is not sufficient evidence of a drop-in replacement. Cross-manufacturer alternatives should be assessed as design changes.
Price and procurement
A catalog specification does not establish stock, lifecycle status or a transaction price. Request a quotation for the exact code and quantity, with delivery and documentation requirements. Confirm the offered packaging and any proposed substitution before accepting the quotation.
What the 7000 density changes—and what the package still limits
The larger logic density is useful only if the required interfaces and implementation fit the selected package. LCMXO2-7000HC-4TG144C combines the 7000 resource set with TG144; another package in the same family can expose a different number of I/Os. Keep the complete ordering code in both the project and the RFQ.
| Resource | How to use it in a selection decision |
|---|---|
| 6,864 LUT4s | Estimate the required functions, then check mapped utilization and timing. Routing and interface constraints can matter before every LUT is consumed. |
| 240 Kbit embedded block RAM | Specify the data width, depth and ports of each buffer. The sum of payload bits alone does not account for block packing or control logic. |
| 256 Kbit user flash | Use it as a distinct nonvolatile resource; review its access, erase and update requirements instead of budgeting it as ordinary working RAM. |
| Two PLLs | List the clock sources, required outputs and pin assignments. Check the exact configuration and timing limits before treating both as available for arbitrary clocks. |
| TG144 maximum 114 user I/Os | Reserve clock, configuration and programming functions used by the design before counting available application pins. |
Resource figures come from the manufacturer selection guide. These are device resources, not a measured throughput, maximum application clock or implementation-fit result.
Using the data sheet for an actual interface
- List the external device, signal direction, voltage standard and expected operating conditions.
- Find that I/O standard's VCCIO and input/output limits in the data sheet. Check the bank assignment and any dedicated pin requirements.
- Define the clock and external timing relationship in the design constraints. Use the exact -4 target rather than a timing table for another speed grade.
- Compile and inspect both setup and hold results. A single family performance example is not a guaranteed frequency for a different path or I/O load.
- Record startup and reconfiguration states for signals that control other circuitry, then verify them on the target board.
The data sheet separates operating conditions, sysIO characteristics, logic timing, PLL timing and configuration timing. Keeping those categories separate prevents a configuration-clock limit from being presented as an application performance limit.
Before selecting a smaller density or another supply variant
A smaller part is a cost candidate only after the project is retargeted and its used pins, memory, clocking and timing are checked. An HE or ZE code also changes the external VCC requirement from the HC supply arrangement. Do not turn a procurement substitution into an undocumented power-design change.
For board implementation, use the 7000HC design-in workflow. It covers a signal worksheet, power planning, programming recovery and first-board acceptance. This overview supplies the selection questions; it does not replace that board review.
Prepare a quotation that can be compared fairly
State the exact code, quantity, delivery destination and required date. If date code, packaging, traceability or inspection documentation matters, list it as a requirement before comparing offers. Confirm whether a proposed alternate code is permitted; leave it pending engineering approval when it is not on the approved BOM.
Compare the written offers on the same quantities and delivery requirements. A historical catalog price does not establish current unit pricing, MOQ, available quantity or shipment timing. The agreed quotation should identify the offered part and commercial conditions clearly.
Request this ordering code
For a quotation, provide LCMXO2-7000HC-4TG144C, quantity, required delivery date, and any packaging, date-code or documentation requirements. Price, availability, lead time and supplied documentation are confirmed in the written quotation.
Find LCMXO2-7000HC-4TG144C · Send an RFQ
Manufacturer documents
- FPGA-DS-02056-4.7, July 2026 — Device selection tables, 3.2 Recommended Operating Conditions, 3.5 Programming/Erase Specifications, Ordering Information
- FPGA-TN-02154-2.2 — 2 Power Supplies, 3 Power Supply Filtering, 6 Programming, 10 True-LVDS Output Pin Assignments
- FPGA-TN-02155-5.0 — 5 Configuration Process, 6 Configuration Ports, 7 Preferences
- MachXO2 family table — Device Selection Guide, 144-pin TQFP I/O count