LCMXO2-1200HC-4TG144C is a Lattice MachXO2 programmable logic ordering code. This overview separates its published resources from the board-specific checks needed for selection and sourcing.
HC power connection: use a nominal 2.5 V or 3.3 V external VCC supply. HC contains an internal regulator; HE and ZE use a 1.2 V external VCC supply. Do not substitute the internal core voltage for the HC board supply. See the power-supply table in the Hardware Checklist.
Specifications
| Item | Specification or design check |
|---|---|
| Logic capacity | 1,280 LUT4s |
| Embedded block RAM / user flash | 64 kbits / 64 kbits |
| PLLs | 1 |
| Package / maximum user I/O | 144-pin TQFP / 107; available user pins depend on enabled functions |
| External VCC | 2.5 V or 3.3 V nominal (HC) |
| Commercial junction temperature | 0°C to +85°C |
| Speed grade | -4; use timing analysis for the exact target |
Resource and package figures: Lattice device-selection table. Electrical limits and temperature: family data sheet. VCCIO must meet the selected I/O-standard limits; it is not interchangeable with VCC.
Supply limits and pinout
The current family data sheet lists 2.375–3.6 V for the recommended HC VCC operating range. Nominal operation is 2.5 V or 3.3 V. Do not confuse this with the 1.14–1.26 V range for the 1.2 V variants. Use the I/O-standard table separately for VCCIO. See recommended operating conditions and sysI/O limits.
Use the manufacturer package drawing and pinout for the exact ordering code when creating a schematic symbol or footprint. The package pin count includes power and configuration functions; it is not the user-I/O count. Reserve programming and clock access before allocating general-purpose signals.
Configuration and implementation
MachXO2 includes internal configuration flash. Choose the intended configuration mode and retain the generated programming file with the project's target selection and build record. A nominal boot-up description is not a substitute for checking the startup timing required by the surrounding system.
Compile the actual design before approving the part. Review pin assignments, logic and memory utilization, clocking and constrained timing. Use the manufacturer's programming-cycle specifications if the application will repeatedly update flash; do not base endurance calculations on an unsourced cycle count.
Alternative parts
Compare the complete proposed ordering code, supply architecture, pin functions and implementation results. A shared TG144 package or a different speed/temperature suffix is not sufficient evidence of a drop-in replacement. Cross-manufacturer alternatives should be assessed as design changes.
Price and procurement
A catalog specification does not establish stock, lifecycle status or a transaction price. Request a quotation for the exact code and quantity, with delivery and documentation requirements. Confirm the offered packaging and any proposed substitution before accepting the quotation.
Read the ordering code before comparing quotations
Keep LCMXO2-1200HC-4TG144C as one complete purchase identifier. The 1200 density, HC supply variant, -4 speed grade, TG144 package and commercial suffix are separate selection decisions. A supplier's shortened “MachXO2-1200” description is not enough to confirm the fitted part.
The manufacturer ordering tables list the exact code as a 1,280-LUT, 144-lead TQFP commercial device with nominal 2.5 V/3.3 V supply. Compare the proposed code character by character with the approved BOM; retain any suffix or revision marker for engineering review.
Turn the specifications into a design budget
| Selection question | Check in the implementation |
|---|---|
| Are there enough pins? | Begin with the TG144 selection-table maximum of 107 user I/Os, then reserve the functions actually used for programming, configuration and clocks. A 144-lead package does not contain 144 freely assignable GPIOs. |
| Does the logic fit? | Compile the intended state machines, counters and interfaces for this exact target. Review the mapped utilization and timing together; synthesis alone is not a place-and-route result. |
| Is memory sufficient? | Distinguish embedded block RAM from nonvolatile UFM. Budget payload bits, port arrangement, width/depth packing and control logic separately. |
| Will the interface meet timing? | Constrain input clocks and external I/O relationships. Inspect the reported worst paths; the -4 suffix is not a complete application-frequency specification. |
The family selection table is the starting resource inventory. Keep the compiler's utilization, pin and timing reports with the schematic as the evidence for your actual design.
Power and pinout: three separate checks
- External core supply: HC uses nominal 2.5 V or 3.3 V VCC. Its internal regulator does not make the board's VCC input a 1.2 V supply.
- I/O-bank supply: identify every used bank and select the standard for its connected device. Apply the data sheet's sysIO limits to that standard; do not assume that the broad supply range makes every input tolerant of every voltage.
- Exact package mapping: reconcile the manufacturer pin file, schematic symbol, footprint and Diamond pin assignment. Check supply/ground, clock and configuration functions before assigning the remaining signals.
During bring-up, record both the static rail values and the device-side startup behavior. Use the Hardware Checklist for the power and programming connections. For a device that is not detected or does not boot, follow the 1200HC troubleshooting sequence.
Which document answers which question?
- Pin and electrical limits: data sheet and the exact package pinout.
- Board connection review: hardware checklist, including clock and configuration access.
- Programming and persistent startup: configuration guide; distinguish a temporary SRAM load from the intended nonvolatile boot operation.
- Possible replacements: use the candidate comparison and approval worksheet, rather than selecting by a shared family name.
Request this ordering code
For a quotation, provide LCMXO2-1200HC-4TG144C, quantity, required delivery date, and any packaging, date-code or documentation requirements. Price, availability, lead time and supplied documentation are confirmed in the written quotation.
Find LCMXO2-1200HC-4TG144C · Send an RFQ
Manufacturer documents
- FPGA-DS-02056-4.7, July 2026 — Device selection tables, 3.2 Recommended Operating Conditions, 3.5 Programming/Erase Specifications, Ordering Information
- FPGA-TN-02154-2.2 — 2 Power Supplies, 3 Power Supply Filtering, 6 Programming, 10 True-LVDS Output Pin Assignments
- FPGA-TN-02155-5.0 — 5 Configuration Process, 6 Configuration Ports, 7 Preferences
- MachXO2 family table — Device Selection Guide, 144-pin TQFP I/O count