Technical review: October 19, 2026.
ICE40HX8K-CB132 is a Lattice iCE40 HX FPGA with 7,680 logic cells in a 132-ball csBGA. This complete ordering code identifies an industrial device. For a buyer comparing quotations, the important checks are the complete part number, package, shipping format and documentation supplied with the offered lot. For an engineer, the first constraints are package-specific I/O, available memory and the configuration circuit.
This reference covers identification, specifications, pinout resources and replacement review. The separate ICE40HX8K-CB132 design-in guide covers board planning and implementation checks.
Ordering code and package
Lattice lists ICE40HX8K-CB132 in the high-performance industrial ordering table of the iCE40 LP/HX Family Data Sheet, FPGA-DS-02029 v4.3, page 46. The CB132 entry is a halogen-free csBGA with 132 balls. Table 2.1 specifies an 8 mm × 8 mm body and 0.5 mm ball pitch. The package code alone does not describe the PCB land pattern, stencil or routing rules; those require the package drawing and an assembly review.
The ordering section states that parts ship in trays unless noted, with TR identifying tape-and-reel where listed. Do not assume this unsuffixed CB132 code is a tape-and-reel order, or append TR without confirming a listed manufacturer ordering code. Ask the supplier to identify the actual shipping format separately from the device identity.
Specifications that apply to this device
| Item | Value and qualification |
|---|---|
| Logic cells | 7,680, each based on a LUT4 and flip-flop |
| Embedded block RAM | 128 Kbits in 32 RAM4K blocks |
| PLLs | 2 for the HX8K CB132 selection |
| Programmable I/O | 95 maximum in CB132; actual availability depends on assigned functions |
| Differential inputs | 12 pairs in CB132, in Bank 3; output support has different requirements |
| Core supply VCC | 1.14–1.26 V recommended operating range; 1.2 V nominal |
| PLL supply VCCPLL | 1.14–1.26 V recommended operating range |
| Active I/O bank and SPI-bank supplies | 1.71–3.46 V recommended range, subject to the selected I/O standard and datasheet notes |
| Industrial operating temperature | −40 to +100 °C junction temperature, rather than ambient temperature |
| Package | 132-ball csBGA, 8 mm × 8 mm, 0.5 mm pitch |
These entries come from Tables 2.1 and 4.2 and the pin summary on page 43 of the data sheet. Absolute maximum ratings are stress limits and should not be used as operating targets. A junction-temperature rating also does not establish the allowable enclosure temperature: board dissipation, ambient conditions and thermal resistance must be considered together.
Table 4.2 also requires the VCCIO pins of unused banks to connect to VCC. Where VCCIO and VCC_SPI use the same voltage, they must use the same supply. Apply these notes together with the selected I/O standard and configuration mode when reviewing the power tree.
The HX8K architecture does not supply the dedicated multiplier-accumulator blocks found in some other iCE40 families. Arithmetic can consume programmable logic, and its resource cost depends on operand widths, pipeline stages and implementation. Likewise, the dedicated SPI configuration interface is not evidence of two hardened application SPI controllers or two hardened I²C controllers. Budget any required application interfaces using the actual HDL and resource report.
The software-support table in Lattice's iCE40 Design Guidelines, page 37, lists iCEcube2 for LP/HX and does not list Radiant support for that family. Confirm the exact device and package in the selected tool release before committing to the development flow.
How to obtain and check the pinout
Use the HX8K pinout file available through the Lattice iCE40 product documentation and select its CB132 column. Cross-check that file against the package drawing and the device selected in the design tool. Do not transfer ball numbers from HX1K, CT256 or CM225, or infer a ball map from the package size.
The HX8K CB132 pin summary divides the general-purpose I/O into Bank 0: 24, Bank 1: 25, Bank 2: 18 and Bank 3: 24, plus four configuration I/O. The resulting 95 is a maximum that includes shared functions. Reserving configuration, clock or PLL connections can reduce the signals available to the application. The summary also lists dedicated inputs separately; they should not be counted as additional bidirectional outputs.
During schematic review, track each ball's function, bank supply, external device voltage and behavior during reset or configuration. Check the schematic symbol and source document naming: VCC_SPI supplies the configuration SPI bank, and some Lattice guidance uses the name SPI_VCC. A voltage-compatible bank does not automatically make a signal tolerant of every external voltage or power-off condition.
Configuration memory and startup
The device supports configuration from internal one-time-programmable NVCM, external SPI flash in master mode, or an external controller in slave SPI mode. Its working SRAM configuration is volatile, but that does not mean external flash is mandatory. NVCM is not an erasable replacement for development flash: decide how field updates and recovery will work before committing to it.
The iCE40 Programming and Configuration technical note, FPGA-TN-02001 v3.5 describes the boot interfaces and sequences. Use its signal directions for the chosen master or slave mode rather than relying on a generic MOSI/MISO label. Include CRESET_B, CDONE and the required supplies in the startup review. Table 4.2 of the data sheet gives different VPP_2V5 conditions for slave SPI, master SPI, NVCM boot and NVCM programming; its name should not be interpreted as an unconditional fixed-voltage instruction.
Application and performance boundaries
Candidate uses include counters, state machines, sensor-interface logic, PWM generation and bounded data buffering. A count of logic cells does not establish a camera count, motor-axis count or guaranteed processing latency. Compile the intended design with its real clock and I/O constraints, then review timing, RAM mapping and resource headroom.
The 128 Kbits of EBR represent 16 KiB of raw storage before allocation and width constraints. As an illustrative calculation, a 640 × 480 image with one byte per pixel needs 307,200 bytes, so that full frame cannot fit in EBR. Streaming or line-buffer architectures may be candidates, but their feasibility depends on the complete design. This is a capacity calculation, not measured hardware performance.
LVDS input support does not establish native MIPI D-PHY, CSI-2, PCIe or USB 3 support. Lattice's differential I/O technical note distinguishes supported input structures from emulated differential outputs and their external components. Define the electrical interface and protocol implementation separately before connecting a camera or display.
Replacement and purchasing review
ICE40HX4K-CB132 is a possible redesign candidate with 3,520 logic cells and 80 Kbits of EBR, rather than half the HX8K's resources. A shared package name does not establish suitability for an existing design. Compare every used pin, power connection, configuration requirement, timing constraint and resource requirement, then rebuild the bitstream for the selected device. An HX8K in another package also requires a package-specific board and pin-assignment review.
For an RFQ, provide the complete ordering code, quantity, required delivery date, accepted shipping format and required lot documentation. Ask for confirmation of current availability, lead time and applicable manufacturer notices. A data-sheet listing or catalog search does not confirm those commercial conditions. You can search WWDParts for ICE40HX8K-CB132 as a starting point for that request.
Common questions
Is CB132 the same as a 0.8 mm-pitch caBGA?
No. This code identifies the 0.5 mm-pitch csBGA option. Other iCE40 package codes have different dimensions and pitches.
Does a PLL frequency establish the whole design's maximum speed?
No. The PLL operating limits, routed internal paths and external interface timing are separate checks. Use constrained timing analysis for the compiled design.
Does the documentation date identify when the chip was launched?
No. The referenced data sheet is v4.3, dated February 2025 on its cover; that revision date does not establish the device's original launch date or the manufacture date of an offered lot.