Designing a board around 10M16SAU169I7G starts with the single-supply pin rules and the U169 package, then the application resource budget. This guide turns those requirements into a schematic, layout and bring-up review. The workflow below is a planning method; it is not a report of a manufactured or tested WWDParts board.
Device resources and design limits
| Item | 10M16SAU169I7G design basis |
|---|---|
| Programmable resources | 16,000 logic elements, 549 Kbit embedded memory and 45 dedicated 18×18 multipliers. |
| Package | 169-ball U169 UBGA, 11 mm × 11 mm, 0.8 mm pitch; 130 GPIO resources before application-specific reservations. |
| Analog conversion | One 12-bit ADC. The single-supply specification gives up to 1 MSPS cumulative sampling. U169 has one dedicated and eight dual-function analog input channels. |
| Main external supply | VCC_ONE uses nominal 3.0 V or 3.3 V. Internal core regulation does not remove VCCA and VCCIO connection requirements. |
| Industrial temperature | −40°C to +100°C junction temperature; board ambient limits still depend on power dissipation and thermal design. |
| External memory | U169 is not listed in the manufacturer's supported 10M16 DDR2/DDR3/LPDDR2 package-width table. |
Sources: MAX 10 device resources; package I/O table; single-supply ADC performance; ADC channel table; recommended operating conditions; supported EMIF packages.
1. Complete the supply and pin worksheet before layout
Obtain the exact U169 pin file, package drawing and single-supply connection guidelines. For each net, record its device pin, bank, required voltage, direction, configuration function and attached peripheral. A GPIO count is not permission to place any signal on any ball. Reserve clock, JTAG, analog and configuration functions before estimating spare I/O.
The S option contains an internal core regulator. Do not copy a dual-supply circuit that expects a separate external 1.2 V core rail. VCC_ONE, VCCA and each VCCIO bank must follow their own connection and filtering rules. An application can share a board rail only where those requirements permit it. Review unused banks and power-up states as well as active interfaces. Use the single-supply pin connection guidelines as the schematic authority.
A useful worksheet has one row per bank and columns for assigned signals, I/O standard, VCCIO, reference requirements, startup state and conflicts. Have the hardware and FPGA constraint files checked together; a schematic review alone will not catch an assignment that places incompatible interfaces in one bank.
2. Plan the analog acquisition path
Choose the U169 analog channels before connecting sensors. The dual-function inputs reduce the digital pin choices when used for acquisition. Read the reference-voltage, input-range, source-impedance and settling conditions in the ADC documentation. Input filtering and buffering follow the source circuit and bandwidth requirements; the converter's presence does not automatically remove the need for an analog front end.
As a planning example, four channels requested at 100,000 samples per second each require 400,000 conversions per second before any additional samples or sequencing overhead. This arithmetic is below a 1,000,000-conversion-per-second aggregate ceiling, but it does not prove the implementation will meet settling, accuracy or latency requirements. Verify the actual sequence and IP configuration. Four channels at 1 MSPS each would exceed that aggregate ceiling.
Start validation with one known input within the documented limits. Record its source, reference and expected code range; then check repeatability and behavior while nearby digital outputs switch. Add the remaining channels and compare their effective rates with the application requirement. These are proposed validation steps, not measured performance claims.
3. Budget memory and clocking before choosing the interfaces
Distinguish embedded RAM, user flash and configuration storage. The product table lists configuration-dependent UFM capacity; a single fixed flash size should not be copied into every design. Use the compiled memory allocation to determine what remains for application data. Clock resources and achievable timing must be checked for the selected package and I7 target. See the manufacturer product table and feature-option table.
If the application needs a DDR frame buffer, stop at the package-selection stage: the published EMIF support table does not list U169. Select a documented supported device/package combination and re-evaluate its supplies and pin budget. Increasing the number of spare GPIOs in an existing U169 design does not establish DDR3 support.
4. Review the PCB with the fabricator and the actual circuit
Use the manufacturer package drawing to check pad geometry, orientation and assembly requirements. Derive escape routing and stack-up from the fabrication process, routing density and electrical requirements. A generic four-layer minimum, a fixed via drill or a universal pad-to-via distance is not a validated fabrication prescription for this design.
Keep return paths and reference planes continuous where required by the signals. Review clock and differential routes, supply distribution, analog-input coupling and the placement of the required decoupling network. Document the reason for any split or filtered supply arrangement. The review should end with an approved stack-up, checked footprint and circuit-specific power-distribution plan, rather than an unsupported list of capacitor distances.
5. Bring up power, JTAG and a small test image
- Inspect the assembled board and check for supply shorts before enabling power. Measure the rails at the device and compare them with the recommended operating conditions.
- Connect the documented TCK, TMS, TDI and TDO signals, cable reference and ground. Identify the target in the programmer before attempting a complex application. Follow the JTAG connection guidelines.
- Compile a small digital test for the exact device with complete pin and timing constraints. Use a safe output and verify its startup behavior before driving external equipment.
- Validate the ADC path and then application logic. Record the tool version, programming-file identifier, constraints, test inputs and observed results.
- For internal-flash deployment, verify cold boot and the selected image mode. If remote upgrade is required, test the documented recovery path on a recoverable development board; dual-image capability is not a guarantee that every update is safe.
Tools and procurement
Quartus edition comparison identifies supported Quartus editions; check the selected release, device package and any IP licensing separately. Estimate power using the actual design and operating conditions instead of a fixed quiescent-power figure. Preserve the resulting reports with the hardware release.
For sourcing, send WWDParts the complete ordering code, quantity and required delivery date, together with any packaging, material declaration or documentation requirements. Price, availability and delivery terms are confirmed in the written quotation. For continued design work, use the MAX 10 FPGA Developer Center.