XC7Z020-2CLG400I combines a dual-core Arm Cortex-A9 processing system with Zynq-7000 programmable logic. For a purchasing or design decision, the complete ordering code matters: the CPU clock limit, available package I/O, temperature grade and board implementation must all match the requirement.
Technical review: October 14, 2026.
Ordering code and device resources
XC7Z020 identifies the Z-7020 device; -2 specifies its speed grade; CLG400 identifies the 400-ball, lead-free wire-bond chip-scale BGA; and I denotes the industrial junction-temperature grade. A quotation should retain every character of this code.
| Item | XC7Z020-2CLG400I |
|---|---|
| Processing system | Dual-core Arm Cortex-A9 |
| PL resources | 85,000 logic cells; 53,200 LUTs; 106,400 flip-flops |
| DSP and block RAM | 220 DSP slices; 140 blocks of 36 Kb, listed as 4.9 Mb |
| Package | 400 balls; 17 × 17 mm body; 0.8 mm pitch |
| Package PL I/O | 125 HR I/O; no HP I/O |
| Industrial operating temperature | −40°C to +100°C junction temperature |
Resource counts and ordering information are in AMD DS190, Zynq-7000 overview. Package dimensions and device-specific I/O counts are in AMD UG865, packaging and pinout.
CPU clock and electrical limits
For speed grade -2, DS187 Table 17 specifies a maximum CPU clock of 766 MHz in 6:2:1 mode, or 600 MHz in 4:2:1 mode. These are configuration-dependent limits, not guaranteed application throughput. Do not use the -3 column's 866 MHz value for this ordering code.
DS187 specifies nominal 1.0 V for VCCPINT, VCCINT and VCCBRAM, with a 0.95–1.05 V operating range for this grade. VCCPAUX and VCCAUX are nominally 1.8 V, with a 1.71–1.89 V range. I/O supplies must match the selected interface standards. Auxiliary rails are not interchangeable with 2.5 V or 3.3 V I/O rails. See AMD DS187, DC and AC switching characteristics, especially Tables 2 and 17 and the power-sequencing sections.
For design sign-off, record the actual clock configuration, implemented timing results and operating conditions together. A processor frequency alone does not establish a control-loop deadline: memory access, interrupts, software scheduling and communication with programmable logic also affect latency.
Pinout: check the device and package together
The CLG400 package exposes 125 PL HR I/O and 128 PS I/O according to UG865. The PS total includes dedicated interface signals; it is not a count of freely interchangeable GPIO. Use the XC7Z020 CLG400 pin file and package drawing when checking a schematic, footprint or supplier substitution. A package name by itself does not establish signal compatibility.
A practical board review should trace each required signal from connector to package ball, then record its bank supply, selected I/O standard and any reference-voltage requirement. Check clock-capable inputs, differential pairs, reset and boot connections before committing to a pin assignment. Resolve unconnected and reserved pins from the manufacturer instructions rather than copying another board's schematic.
Choosing a useful PS and PL workload split
The processing system can handle software control while programmable logic implements custom datapaths. Z-7020 has no dedicated multi-gigabit transceivers. The presence of programmable I/O should not be treated as support for a transceiver-dependent protocol. The device architecture is described in DS190.
As a design example, a sensor-processing system could put filtering in logic and configuration or reporting in software. Start with the input sample rate, word width and latency target, then budget the buffering and transfers between those stages. This is an architectural option, not evidence that a particular sample rate or control deadline has been achieved.
Check resource utilization after implementation rather than estimating capacity from logic-cell count alone. A design may run out of a particular memory arrangement, routing capacity or suitable I/O before it exhausts the headline logic resources. Include external converters, interface devices and memory in the board requirements where the application needs them.
Example: budgeting a sample buffer
Suppose a design reserves 16 BRAM blocks and maps 32 Kib of ordinary data per block, leaving the additional parity-bit capacity outside this buffer budget. The assumed payload capacity is 16 × 32 × 1,024 ÷ 8 = 65,536 bytes, or 64 KiB. For one channel producing 20,000 samples per second at two bytes per sample, that holds 65,536 ÷ 40,000 = 1.6384 seconds of samples before allowing for headers, alignment or reserved space. This is a capacity calculation under stated assumptions, not a measured capture duration. Confirm the chosen memory configuration and implementation report; the 36 Kb block rating includes parity capacity and should not be treated automatically as a byte-addressable software buffer.
Minimum boot and DDR acceptance checks
- Record the fitted device, board revision, selected boot source and exact boot-image version. Verify power, reset and reference-clock behavior against the device requirements before interpreting software failures.
- Confirm that the boot configuration and initialization settings match the actual board and external memory. Keep a serial-console log from a cold start through application launch, and repeat with the intended reset sequence.
- Run a memory test over a deliberately reserved DDR region so that it cannot overwrite running software. Record tested addresses, patterns, clock settings and results; a successful small memory test does not prove the entire memory interface is qualified.
- Exercise the intended PS-to-PL transfers and application workload, including buffer-full and recovery behavior. Record failures and repeat at the board's specified operating corners before release.
Power and thermal planning
A useful power estimate needs the intended clocks, switching activity, resource use, I/O loads and thermal environment. Run a device-specific estimate, refine it with implementation data and validate the assembled board under representative workloads. There is no single wattage that describes every XC7Z020 design.
The industrial temperature limit is a junction limit, not a permissible ambient temperature. Estimate the thermal margin for the enclosure and board, then determine whether airflow or additional cooling is needed. UG865 explains the package thermal considerations; a heatsink is not a universal requirement or a substitute for checking the actual operating conditions.
Alternatives require engineering approval
UG865 lists XC7Z010 in CLG400, but it has fewer available PL I/O than XC7Z020 in that package. It does not list XC7Z015 in CLG400. Do not approve a supposed XC7Z015-2CLG400I replacement from a similarity search.
For any proposed alternative, compare the complete pin assignment, resource fit, timing, power rails and temperature range. Rebuild and verify the programmable-logic design and review the software and boot configuration. A different speed grade needs a timing review even when the package is unchanged. A different device family should be evaluated as a redesign candidate.
What to include in an RFQ
- Exact ordering code, quantity and required delivery date.
- Whether substitutions are prohibited or require written engineering approval.
- Required packaging, date-code restrictions and traceability documentation.
- Any compliance documentation and incoming-inspection requirements needed for the purchase.
Obtain current lifecycle information, availability, price and delivery terms for the specific offer. A datasheet does not establish stock, lead time or the provenance of a supplied lot. For assembly planning, use the actual package label and handling instructions to establish moisture exposure and reflow requirements.
Manufacturer references
- DS190, Zynq-7000 SoC overview, version 1.11.1, July 2, 2018.
- DS187, electrical and switching specifications, version 1.21, December 1, 2020.
- UG865, packaging and pinout, version 1.9, July 28, 2021.
These dates identify the referenced document revisions. Confirm applicable errata and document updates before design release.