Designing a board around XC7A35T-1CPG236C begins with a pin plan, a power budget and a boot strategy. Its 10 × 10 mm, 0.5 mm-pitch package is compact, but the device name does not determine a universal regulator, capacitor recipe or PCB layer count. This guide focuses on decisions to settle before releasing the schematic and layout.
Freeze the interfaces before the footprint
Create the exact FPGA project and assign the required clocks, configuration pins, user interfaces and any GTP channels. Run the relevant tool checks early. The package has 106 HR user I/O and two GTP channels, which must be assessed by bank and dedicated function. Reserving 106 arbitrary signal names does not constitute a valid pin plan.
Review the package drawing and ball map with the PCB fabricator and assembly provider. Select pad geometry, escape routing, via process and stack-up as a complete design. Neither “0.8 mm dog-bone routing is sufficient” nor “every design requires microvias” is an accurate rule for CPG236. Include return paths, decoupling access and inspection requirements in the discussion.
Build a rail budget
| Supply group | Design action |
|---|---|
| VCCINT and VCCBRAM | Plan the nominal 1.0 V operation of this -1 part; estimate configured current and startup requirements. |
| VCCAUX | Provide the specified nominal 1.8 V auxiliary supply. |
| VCCO banks | Choose voltages from the actual supported I/O standards and check configuration-bank restrictions. |
| GTP and XADC connections | Follow the used and unused resource requirements; do not leave supply decisions to a generic three-rail diagram. |
Use DS181: operating conditions and sequencing for operating limits and sequencing, and UG483: PCB design and power distribution for power-distribution design. When VCCINT and VCCBRAM use the same recommended voltage, DS181 permits a shared supply. Capacitor placement and rail impedance must be evaluated with the current spectrum, regulator behavior and layout. A nominal current rating alone does not establish transient performance or stability.
Estimate power from clocks, utilization, I/O loading and activity, then refine it with implementation data and measurements. Keep startup current separate from average configured current. Thermal estimates need ambient conditions, airflow, PCB and enclosure assumptions; there is no universal wattage threshold that decides whether this board needs a heatsink.
Select and size configuration memory
For autonomous SPI boot, select the flash by voltage, commands, addressing, supported interface and tool support as well as capacity. For host-loaded systems, define the host's configuration sequence and recovery path instead. Retain suitable JTAG access for bring-up and service.
UG470: configuration and device ID codes gives 17,536,096 bits for the XC7A35T uncompressed configuration stream, equivalent to 2,192,012 bytes. Its configuration-memory table specifies a 32 Mb minimum flash density for this device. A 32 Mb or 64 Mb flash is therefore not inherently too small for one configuration image.
For illustration, two streams of that stated size total 4,384,024 bytes before placement, headers and other stored content. A 32 Mb flash has 4,194,304 bytes of nominal capacity, so that particular uncompressed two-image arrangement exceeds it. A 64 Mb device has 8,388,608 bytes, but the final selection still depends on the generated files, erase boundaries, reserved areas, boot commands and recovery design. Validate actual offsets and end addresses instead of multiplying only a typical compressed image size.
Check configuration voltages explicitly
Record VCCO_0, CFGBVS and the supplies for any multifunction configuration pins. UG470 specifies the allowable combinations. For 2.5 V or 3.3 V configuration-bank operation, CFGBVS is tied to VCCO_0; for the applicable lower-voltage arrangement it is tied to ground. The flash, programmer reference and pull-ups must agree with the selected scheme.
Check the mode pins and startup behavior against the actual boot mode. A flash that can be programmed through an attached cable may still fail autonomous cold boot because of mode, bus-width, reset or timing assumptions.
Define measurable release checks
- Archive the exact pin map and design-rule reports with the schematic revision.
- Capture rail startup, shutdown and maximum-load behavior at the FPGA.
- Verify boot from an empty or invalid source fails safely, then verify the intended recovery procedure.
- Run the memory and external-interface tests under representative sustained traffic.
- Measure temperature and power within the intended operating environment.
- Record programming files, flash layout and production-test steps as controlled release artifacts.
This work produces a board-specific design basis. It also gives purchasing a stable full ordering code and documentation requirement, instead of an open-ended request for a “similar Artix-7.”
Sources and next steps
- DS180: device resources and package combinations
- DS181: operating conditions and sequencing
- UG475: packaging and pinout
- UG483: PCB design and power distribution
- UG470: configuration and device ID codes
Use the bring-up troubleshooting guide.
For sourcing, send the full ordering code, quantity, required date and documentation requirements through our RFQ form. Availability, price and delivery are confirmed in the written quotation.
Technical content reviewed against manufacturer documentation on October 12, 2026. Design examples are calculations and planning guidance, not measured performance or a qualified reference design.