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ADL5561ACPZ-R7 Functional Block Diagram and Overview (Source: Analog Devices Datasheet)
The ADL5561ACPZ-R7 is a 2.9 GHz ultralow distortion RF/IF differential amplifier manufactured by Analog Devices. Built on a high-speed SiGe BiCMOS process, this device delivers exceptional linearity and noise performance, making it an optimal ADC driver for wireless infrastructure, radar, and precision instrumentation applications. The ADL5561 features pin-selectable gain settings of 6 dB, 12 dB, and 15.5 dB, with a typical supply current of only 40 mA from a 3.3 V rail. Its compact 16-lead LFCSP package (3 mm × 3 mm) and wide operating temperature range of −40°C to +85°C make it suitable for space-constrained, high-reliability designs.
Table of Contents
1. Overview and Core Features
The ADL5561 is a fully differential amplifier optimized for RF and IF signal chains, principally as an ADC driver in receiver front-end designs. It accepts either differential or single-ended inputs and produces a differential output, eliminating the need for external balun transformers in many topologies. The device integrates on-chip feedback and feed-forward resistors that enable three discrete gain configurations—6 dB, 12 dB, and 15.5 dB—selected by pin strapping the VIP and VIN terminals. For single-ended input configurations, the corresponding gains are 5.6 dB, 11.1 dB, and 14.1 dB. An external series input resistor can further extend gain flexibility down to 0 dB.
Key performance figures include an input-referred noise density of 2.1 nV/√Hz (at 12 dB gain), harmonic distortion of −86 dBc HD2 and −88 dBc HD3 at 100 MHz, and an IMD3 of −95 dBc at 100 MHz. The ENBL pin provides a low-power shutdown mode drawing only 3 mA, with high input-to-output isolation for TDD switching applications. A VCOM pin allows the user to set the output common-mode voltage independently, simplifying the interface to ADCs with varying common-mode requirements.
ADL5561ACPZ-R7 Pin Configuration and LFCSP-16 Package Drawing (Source: Analog Devices Datasheet)
2. Specifications and Parameter Table
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices (ADI) |
| −3 dB Bandwidth | 2.9 GHz (at AV = 6 dB) |
| Gain Settings (Differential Input) | 6 dB / 12 dB / 15.5 dB (pin-selectable) |
| Gain Settings (Single-Ended Input) | 5.6 dB / 11.1 dB / 14.1 dB |
| Input Noise Density | 2.1 nV/√Hz RTI (at AV = 12 dB) |
| HD2 / HD3 (100 MHz) | −86 dBc / −88 dBc |
| IMD3 (100 MHz) | −95 dBc |
| Slew Rate | 9800 V/µs |
| Supply Voltage | 3.0 V to 3.6 V (typ. 3.3 V) |
| Supply Current | 40 mA typical / 3 mA in disable |
| Package | 16-Lead LFCSP (3 mm × 3 mm), CP-16-27 |
| Operating Temperature | −40°C to +85°C |
| Process Technology | High-speed SiGe BiCMOS |
| Ordering Suffix | ACPZ-R7 (7″ Tape & Reel, 1500 pcs) |
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Check ADL5561ACPZ-R7 Stock3. Architecture and Block Diagram
Internally, the ADL5561 consists of a high open-loop gain differential amplifier core with integrated gain-setting resistor networks. Two pairs of feed-forward resistors (connected at the VIP1/VIP2 and VIN1/VIN2 pins) form a resistive ladder that determines the closed-loop gain. By selectively connecting or floating these pins, engineers can configure the three fixed gain settings without any external components.
The output stage drives a differential load (nominal 200 Ω) and includes an independent output common-mode feedback loop controlled by the VCOM pin. This architecture allows the ADL5561 to interface directly to ADCs with different common-mode voltage requirements. The differential input impedance varies with gain setting: approximately 400 Ω at 6 dB, 200 Ω at 12 dB, and 133 Ω at 15.5 dB gain, enabling straightforward impedance matching. The device supports both AC-coupled and DC-coupled configurations at both input and output, providing maximum design flexibility in wideband receiver chains.
ADL5561ACPZ-R7 Typical Application Circuit and ADC Interface (Source: Analog Devices Datasheet)
4. Video: ADC Driver Amplifier Design
This video covers the methodology for selecting and verifying a driver amplifier for high-speed ADC applications—directly applicable to designs using the ADL5561. Key topics include impedance matching, distortion analysis, and settling-time verification when interfacing differential amplifiers to precision converters.
5. Equivalents, Cross-Reference, and Lifecycle
The ADL5561ACPZ-R7 carries an Active production status from Analog Devices with no announced end-of-life date. For designs requiring pin-compatible alternatives with different bandwidth or distortion profiles, engineers should consider:
- ADL5562 — A pin-compatible sibling with 6 GHz bandwidth and higher linearity at elevated frequencies. It is a direct drop-in replacement for applications requiring wider IF bandwidth.
- ADL5565 — Another pin-compatible differential amplifier in the same family, optimized for 6 GHz operation with higher OIP3 performance, targeting demanding multi-carrier receiver architectures.
- AD8352 — An earlier-generation differential amplifier from ADI with externally adjustable gain (0 to 24 dB) and 2 GHz bandwidth, suitable for applications requiring continuous gain control.
When evaluating alternatives, verify that the replacement device meets HD2, HD3, and IMD3 requirements at your specific IF frequency. The ADL5562 offers a nearly identical pinout and can serve as a higher-bandwidth substitute in most designs. Check ADL5561ACPZ-R7 Inventory & Pricing at WWDParts for current lead times and stock availability.
6. Frequently Asked Questions (FAQ)
Q1: What is the ADL5561ACPZ-R7, and what applications is it designed for?
The ADL5561ACPZ-R7 is a 2.9 GHz ultralow distortion differential amplifier from Analog Devices, primarily designed as an ADC driver for high-speed data converters in wireless base stations, radar receivers, and precision instrumentation. Its low noise floor of 2.1 nV/√Hz and distortion performance (−88 dBc HD3 at 100 MHz) make it particularly effective when driving 12-bit to 16-bit ADCs at intermediate frequencies up to 300 MHz. The device supports both single-ended-to-differential and fully differential signal chain topologies.
Q2: How do I select the gain of the ADL5561?
The ADL5561 provides three discrete gain settings selected by pin strapping. For 6 dB gain, connect the input signal to VIP1 and VIN1 while leaving VIP2 and VIN2 floating. For 12 dB gain, connect to VIP2 and VIN2 while floating VIP1 and VIN1. For maximum 15.5 dB gain, connect the input to both VIP1+VIP2 and VIN1+VIN2 simultaneously. For single-ended inputs, these values reduce to 5.6 dB, 11.1 dB, and 14.1 dB respectively. External series resistors at the input can further reduce the effective gain to as low as 0 dB for custom gain requirements.
Q3: What is the difference between ADL5561 and ADL5562?
The ADL5562 is a higher-bandwidth variant in the same product family, offering a −3 dB bandwidth of 6 GHz compared to the ADL5561's 2.9 GHz. Both devices share the same 16-lead LFCSP pinout and gain configuration methodology. The ADL5562 draws slightly more supply current (approximately 56 mA vs. 40 mA) and achieves better distortion performance at frequencies above 200 MHz. For IF sampling applications below 200 MHz, the ADL5561 typically offers equivalent SFDR performance at lower power consumption, making it the preferred choice for power-sensitive designs.
Q4: What are the power supply decoupling requirements for the ADL5561ACPZ-R7?
Analog Devices recommends placing 100 pF and 0.1 µF bypass capacitors as close as possible to each VCC pin, with short, wide traces to the ground plane. A bulk 10 µF tantalum capacitor should be placed near the device for low-frequency supply filtering. The exposed paddle on the bottom of the LFCSP package must be soldered to a solid ground plane with multiple thermal vias to ensure both thermal dissipation and low-impedance grounding. The power supply should be regulated to 3.3 V ±10%, and supply ripple should be minimized to prevent modulation of the output signal.
Q5: Can the ADL5561 accept single-ended inputs, and how does this affect performance?
Yes. The ADL5561 can convert a single-ended input to a differential output without requiring an external balun transformer. In this configuration, the unused input pin is AC-coupled to ground through a capacitor. The gain is reduced by approximately 0.4 dB to 1.4 dB compared to the differential input case because only half the input impedance is driven. The input impedance in single-ended mode is half the differential value (e.g., 200 Ω differential becomes 100 Ω single-ended at 6 dB gain). Amplitude and phase balance between the differential outputs remain within typical specifications, enabling clean ADC driving without significant even-order distortion degradation.
Q6: What is the VCOM pin used for on the ADL5561?
The VCOM pin controls the output common-mode voltage of the ADL5561. By default, the internal bias sets the output common-mode to approximately VCC/2 (about 1.65 V on a 3.3 V supply). Engineers can override this by driving the VCOM pin with an external voltage source or connecting it to the ADC's common-mode output reference. This feature is critical when interfacing with ADCs that have specific common-mode input requirements different from VCC/2. The VCOM input has a high impedance and should be bypassed with a 0.1 µF capacitor to ground to maintain stability and reject noise on the common-mode control loop.
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Alan Carter, Senior Hardware Engineer
Alan has over 15 years of experience in embedded systems design, specializing in RF signal chain optimization, high-speed ADC interface design, and global semiconductor supply chain management. He frequently contributes technical teardowns and architecture comparisons.
