ADL5561ACPZ-R7: Gain, Common Mode and ADC Driver Design

· Published by WWDParts

The ADL5561ACPZ-R7 is a differential RF/IF amplifier used in analog signal paths, including ADC-driver stages. It accepts differential or single-ended excitation and provides a differential output. Successful ADC interfacing depends on more than its headline bandwidth: gain strapping, source loading, common-mode voltage, filtering and the converter’s sampling input must work together. This guide develops those checks without assuming that a nominal gain setting is the end-to-end gain of a complete receiver.

Key specifications and pin functions

Bandwidth 2.9 GHz, −3 dB, at 6 dB gain under specified conditions
Supply and typical current 3.0–3.6 V; 40 mA typical quiescent current
Differential gain options 6 dB, 12 dB or 15.5 dB, selected by input connections
Single-ended gain options 5.6 dB, 11.1 dB or 14.1 dB
Package 16-lead, 3 × 3 mm LFCSP
Operating temperature −40 to +85 °C
Control pins Pin 9 VCOM; pin 12 ENBL
Output pins Pin 10 VON; pin 11 VOP

Source: ADI ADL5561 product documentation and ADI ADL5561 datasheet, Rev. G. R7 identifies an ordering format; retain the complete suffix on the purchasing record instead of treating packaging shorthand as an electrical performance grade.

Gain strapping changes the source load

The 6 dB connection uses VIP1/VIN1, 12 dB uses VIP2/VIN2, and 15.5 dB straps the corresponding input pairs together. The approximate low-frequency differential input resistances are 400 Ω, 200 Ω and 133 Ω, respectively. ADI AN-1098: Differential Driver and ADC Interface Design. These are analog signal connections, not a digital gain-control register.

Make a gain worksheet that starts at the signal source and ends at the ADC pins. Include source resistance, input matching, amplifier gain and output-filter insertion loss. Changing the strap while keeping the same resistor network may alter both gain and match. Check actual node voltages rather than relying only on the generator’s power setting.

For a simplified differential resistive example, place 200 Ω total series resistance ahead of a 200 Ω amplifier input. The resulting divider is 200/(200 + 200) = 0.5, or −6.02 dB. Combined with a nominal 12 dB stage, the source-to-amplifier-output voltage gain is about 5.98 dB before any further loading or output attenuation. This calculation assumes an ideal source and ignores reactance; it is not a broadband matching design.

Set common mode as well as differential swing

VCOM sets the input and output common-mode bias; without an external reference they settle around midsupply. Changing VCOM therefore requires reviewing both sides of the signal path. ADI ADL5561 datasheet, Rev. G. A direct connection to an ADC common-mode source must be assessed against both devices’ permitted conditions and the way the input source is coupled.

For an illustrative 2 V peak-to-peak differential sine wave centered on 1.65 V, equal antiphase outputs each have a 1 V peak-to-peak swing. Each output therefore moves from approximately 1.15 V to 2.15 V. Verify both individual pin voltages and the differential waveform. A scope measurement on only one output can lead to a factor-of-two swing error.

If DC information must pass through the path, explicitly include the source’s DC common mode in the review. If AC coupling is used, calculate its low-frequency response with the effective input or load resistance. A capacitor chosen only because it appears on an evaluation board may not meet a different passband requirement.

Why a fast amplifier still needs an antialias interface

AN-1098 treats the driver, filter, impedance transformation and sampling ADC as one interface. It explains how unwanted wideband noise and a converter’s time-varying input load affect the result. ADI AN-1098: Differential Driver and ADC Interface Design. Follow that method for the chosen converter rather than assuming that two differential pins can always be connected directly.

Write the wanted band, allowable passband loss, stopband attenuation and ADC full-scale swing before selecting components. Include filter insertion loss in the gain budget and include component tolerance and parasitics in simulation. Measure the response on the assembled PCB; a nominal filter design can shift when its source or termination differs from the intended value.

A simple noise estimate illustrates why bandwidth matters. Assume, only for calculation, a flat 2.1 nV/√Hz input-referred density over a 20 MHz equivalent noise bandwidth. The integrated value is 2.1 nV/√Hz × √20,000,000 Hz, approximately 9.39 µV rms. Increasing the bandwidth fourfold doubles that contribution. This excludes resistor noise, ADC noise, frequency dependence and transfer-function weighting; combine independent contributions by root-sum-square, not by simply adding their rms amplitudes.

Power, enable and layout checks

Using the typical 40 mA figure at 3.3 V gives 132 mW of quiescent supply power. Treat it as a nominal planning point, then account for operating conditions and the rest of the signal chain. Do not replace the specified 3.0–3.6 V range with a rounded “3.3 V ±10%” requirement, which would extend to 3.63 V.

The datasheet’s basic connection uses local supply and VCOM decoupling and requires the exposed paddle to connect to a low-impedance thermal and electrical ground. ADI ADL5561 datasheet, Rev. G. Review the return paths and differential symmetry with the PCB layout, including test pads and any output filter. Test recovery after enable changes under the real downstream load; a settled DC voltage alone does not prove that the signal path has recovered to its required accuracy.

Validation and proposed substitutions

  • Check gain and common mode at low level before sweeping toward the ADC full-scale input. Record source and load impedances with the result.
  • Measure distortion at the intended frequency and amplitude. A harmonic figure from another frequency or gain setting is not a universal specification.
  • Repeat with the actual ADC clock running and inspect both spectrum and time-domain clipping. Compare against an otherwise equivalent test arrangement.
  • Review the complete pinout, supply, gain network and thermal budget for a candidate replacement. ADL5562 lists a 3.3 GHz bandwidth; verify its electrical conditions against the intended circuit before approving a substitution.

The comparison basis is ADI ADL5562 product documentation. Keep the acceptance criteria tied to the actual converter interface and application bandwidth.

Ordering and manufacturer references

For ADL5561ACPZ-R7, send the complete ordering code, quantity, required delivery date and documentation requirements through the WWDParts RFQ list. Price, availability and delivery terms are confirmed in the written quotation. Review any proposed substitution against the released circuit and application requirements.

Technical content reviewed October 14, 2026. Calculations are illustrative design estimates with stated assumptions; they are not measurements or qualification results.

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